公开(公告)号：US20240136269A1

公开(公告)日：2024-04-25

申请号：US17968830

申请日：2022-10-18

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/64 ,  H01L25/00 ,  H01L25/065 ,  H01L25/16 ,  H01L25/18

CPC classification number: H01L23/49833 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/642 ,  H01L25/0655 ,  H01L25/162 ,  H01L25/18 ,  H01L25/50 ,  H01L24/32

Abstract: A device is provided, including a package substrate including at least one opening extending through the package substrate, and an interconnect structure including a first segment and a second segment. The first segment may extend under a bottom surface of the package substrate and may further extend beyond a footprint of the package substrate. The second segment may extend vertically from the first segment and may extend at least partially through the at least one opening of the package substrate.

公开(公告)号：US20240071934A1

公开(公告)日：2024-02-29

申请号：US17894200

申请日：2022-08-24

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Seok Ling LIM

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L23/64 ,  H01L25/065

CPC classification number: H01L23/5381 ,  H01L21/4846 ,  H01L23/5386 ,  H01L23/642 ,  H01L24/16 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/14335 ,  H01L2924/1436 ,  H01L2924/3511

Abstract: The present disclosure is directed to semiconductor packages incorporating composite or hybrid bridges that include first and second interconnect bridges positioned on a substrate and a power corridor with a plurality of vertical channels positioned on the substrate between the first and second interconnect bridges, wherein the power corridor integrally joins the first interconnect bridge to the second interconnect bridge.

公开(公告)号：US20240071856A1

公开(公告)日：2024-02-29

申请号：US17895102

申请日：2022-08-25

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/367 ,  H01L23/373

CPC classification number: H01L23/3675 ,  H01L23/3736

Abstract: The present disclosure is directed to an electronic assembly and method of forming thereof. The electronic assembly may include a substrate and a first die with first and second opposing surfaces. The first die may be coupled to the substrate at the first surface. At least one first trench may extend partially through the first die from the second surface. A stiffener may be attached to the substrate. The stiffener may have a cavity that accommodates the first die, in which the second surface of the first die faces the stiffener. A thermally conductive layer may be positioned between the stiffener and the first die. The conductive layer at least partially fills the at least one first trench.

公开(公告)号：US20230253295A1

公开(公告)日：2023-08-10

申请号：US18132801

申请日：2023-04-10

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Choong Kooi CHEE ,  Jackson Chung Peng KONG ,  Wai Ling LEE ,  Tat Hin TAN

IPC: H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822

CPC classification number: H01L23/481 ,  H01L25/16 ,  H01L24/09 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/17 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US20230112520A1

公开(公告)日：2023-04-13

申请号：US17498008

申请日：2021-10-11

Applicant: Intel Corporation

Inventor： Yee Lun ONG ,  Teong Guan YEW ,  Bok Eng CHEAH ,  Jackson Chung Peng KONG

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

Abstract: The present disclosure relates to an electronic assembly including a package substrate with a first surface and an opposing second surface; a first interconnect disposed in the package substrate and extending between the first and the second surfaces; and a second interconnect disposed in the package substrate and extending between the first and the second surfaces; wherein the first interconnect comprises a first recessed side wall and the second interconnect is arranged adjacent the first recessed side wall.

公开(公告)号：US20220077113A1

公开(公告)日：2022-03-10

申请号：US17089741

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Seok Ling LIM

IPC: H01L25/065 ,  H01L27/06 ,  H01L23/367 ,  H01L23/538 ,  H01L21/50

Abstract: A chip package includes a substrate; a first chip including thermal VIAs, wherein the first chip is coupled to the substrate; a conductive frame at least partially surrounding the first chip and coupled to the substrate, wherein the first chip and the conductive frame have a height that is substantially the same, wherein an exposed substrate surface is covered in a layer of encapsulation material having the same height; a second chip positioned on a first portion the first chip surface in such a way to expose at least a portion of the first chip surface, wherein the at least one exposed portion includes thermal VIAs; and at least one conductive plate positioned on the at least one exposed portion, wherein the conductive plate is coupled to the conductive frame and the thermal VIAs of the first chip.

公开(公告)号：US20220068821A1

公开(公告)日：2022-03-03

申请号：US17090919

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Seok Ling LIM ,  Jenny Shio Yin ONG ,  Jackson Chung Peng KONG ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L23/552 ,  H01L21/48

Abstract: A device is provided, including a package substrate, a first interposer including a plurality of first vias extending through the first interposer, and a second interposer including a plurality of second vias extending through the second interposer. The first interposer and the second interposer may be arranged on the package substrate and may be spaced apart from each other.

公开(公告)号：US20210384130A1

公开(公告)日：2021-12-09

申请号：US16987405

申请日：2020-08-07

Applicant: Intel Corporation

Inventor： Bok Eng CHEAH ,  Yang Liang POH ,  Kooi Chi OOI

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: The present disclosure relates to a semiconductor package that may include a substrate. The substrate may have a top surface and a bottom surface. The semiconductor package may include an opening in the substrate. The semiconductor package may include a bridge disposed in the opening. The bridge may have an upper end at the top surface of the substrate and a lower end at the bottom surface of the substrate. The semiconductor package may include a first die on the top surface of the substrate at least partially extending over a first portion of the upper end of the bridge. The semiconductor package may include a second die on the bottom surface of the substrate at least partially extending over the lower end of the bridge. The bridge may couple the first die to the second die.

公开(公告)号：US20190215953A1

公开(公告)日：2019-07-11

申请号：US16327453

申请日：2016-10-01

Applicant: Intel Corporation

Inventor： Khang Choong YONG ,  Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Stephen H. HALL

IPC: H05K1/02

CPC classification number: H05K1/0228 ,  H05K1/0225 ,  H05K1/0253 ,  H05K1/0296 ,  H05K2201/093

Abstract: Embodiments are generally directed to a mutual inductance suppressor for crosstalk immunity enhancement. An embodiment of a printed circuit board includes a first signal trace and a second signal trace on a first layer, wherein the first signal trace and second signal trace are non-intersecting; a second layer below the first layer, the second layer including a voltage reference plane; and a mutual inductance suppressor in the voltage reference plane, the mutual inductance suppressor including a serpentine portion of the voltage reference plane between the first signal trace and the second signal trace.

公开(公告)号：US20180358292A1

公开(公告)日：2018-12-13

申请号：US15974493

申请日：2018-05-08

Applicant: Intel Corporation

Inventor： Jackson Chung Peng KONG ,  Bok Eng CHEAH ,  Wen Wei LUM ,  Mooi Ling CHANG ,  Ping Ping OOI

IPC: H01L23/522 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/5223 ,  H01L23/315 ,  H01L24/09 ,  H01L2224/0233

Abstract: Over-molded IC package assemblies including an in-mold capacitor. In some embodiments, an over-molded package assembly includes a IC chip or die coupled to one or more metal distribution layer or package substrate. A molding compound encapsulates at least the IC chip and one or more capacitors are fabricated within the molding compound. The capacitors may include two or more metal plates separated by an intervening dielectric material, all of which are embedded within a trench in the molding compound. Individual ones of the capacitor plates may physically contact a conductive land of the package redistribution layer or package substrate, for example to tie the plates to a ground plane and power plane, or two supply rails, in a decoupling capacitor application.