公开(公告)号：US10601738B2

公开(公告)日：2020-03-24

申请号：US16024774

申请日：2018-06-30

Applicant: Intel Corporation

Inventor： Bruce Richardson ,  Chris MacNamara ,  Patrick Fleming ,  Tomasz Kantecki ,  Ciara Loftus ,  John J. Browne ,  Patrick Connor

IPC: H04L12/861 ,  H04L12/879

Abstract: Technologies for buffering received network packet data include a compute device with a network interface controller (NIC) configured to determine a packet size of a network packet received by the NIC and identify a preferred buffer size between a small buffer and a large buffer. The NIC is further configured to select, from the descriptor, a buffer pointer based on the preferred buffer size, wherein the buffer pointer comprises one of a small buffer pointer corresponding to a first physical address in memory allocated to the small buffer or a large buffer pointer corresponding to a second physical address in memory allocated to the large buffer. Additionally, the NIC is configured to store at least a portion of the network packet in the memory based on the selected buffer pointer. Other embodiments are described herein.

公开(公告)号：US20190097948A1

公开(公告)日：2019-03-28

申请号：US15718836

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： John J. Browne ,  Christopher MacNamara ,  Tomasz Kantecki ,  Barak Hermesh ,  Sean Harte ,  Andrey Chilikin ,  Brendan Ryan ,  Bruce Richardson ,  Michael A. O'Hanlon ,  Andrew Cunningham

IPC: H04L12/935 ,  H04L12/861

Abstract: An apparatus, including: a hardware platform; logic to execute on the hardware platform, the logic configured to: receive a batch including first plurality of packets; identify a common attribute of the batch; perform batch processing on the batch according to the common attribute; generate a hint for the batch, the hint comprising information about the batch to facilitate processing of the batch; and forward the batch to a host platform network interface with the hint.

公开(公告)号：US20180103129A1

公开(公告)日：2018-04-12

申请号：US15677564

申请日：2017-08-15

Applicant: Intel Corporation

Inventor： Cristian Florin F. Dumitrescu ,  Namakkal N. Venkatesan ,  Pierre Laurent ,  Bruce Richardson

IPC: H04L29/06 ,  H04L12/743 ,  H04L12/64

CPC classification number: H04L69/22 ,  H04L12/6418 ,  H04L45/7453

Abstract: Technologies for packet flow classification on a computing device include a hash table including a plurality of hash table buckets in which each hash table bucket maps a plurality of keys to corresponding traffic flows. The computing device performs packet flow classification on received data packets, where the packet flow classification includes a plurality of sequential classification stages and fetch classification operations and non-fetch classification operations are performed in each classification stage. The fetch classification operations include to prefetch a key of a first received data packet based on a set of packet fields of the first received data packet for use during a subsequent classification stage, prefetch a hash table bucket from the hash table based on a key signature of the prefetched key for use during another subsequent classification stage, and prefetch a traffic flow to be applied to the first received data packet based on the prefetched hash table bucket and the prefetched key. The computing device handles processing of received data packets such that a fetch classification operation is performed by the flow classification module on the first received data packet while a non-fetch classification operation is performed by the flow classification module on a second received data packet.

公开(公告)号：US20230102067A1

公开(公告)日：2023-03-30

申请号：US18076120

申请日：2022-12-06

Applicant: Intel Corporation

Inventor： Bruce Richardson ,  Niall McDonnell ,  Harry Van Haaren

IPC: G06F3/06

Abstract: An accelerator device may generate and submit descriptors to be processed by the accelerator device. Software executing on a processor may submit descriptors to the accelerator device to be processed in parallel.

公开(公告)号：US11489791B2

公开(公告)日：2022-11-01

申请号：US16177262

申请日：2018-10-31

Applicant: Intel Corporation

Inventor： Niall D. McDonnell ,  Bruce Richardson ,  John Mangan ,  Harry Van Haaren ,  Ciara Loftus ,  Brian A. Keating

IPC: G06F13/10 ,  H04L49/00 ,  G06F9/54 ,  H04L49/9005

Abstract: Examples include a method of switching a packet by a virtual switch by receiving a system call to transmit a packet from a first application running in a first container on a first core, determining a destination for the packet, obtaining a buffer in an application memory space of the destination, copying the packet to the destination application memory space, and writing an entry for the packet to a queue assigned to the destination, the destination queue being in a queue manager. The packet may then be obtained by an entity at the destination.

公开(公告)号：US10445271B2

公开(公告)日：2019-10-15

申请号：US14987676

申请日：2016-01-04

Applicant: Intel Corporation

Inventor： Ren Wang ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Yipeng Wang ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs ,  Andrew J. Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson

IPC: G06F13/37 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/0868 ,  G06F12/04 ,  G06F9/38

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US20190044879A1

公开(公告)日：2019-02-07

申请号：US16023743

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Bruce Richardson ,  Andrew Cunningham ,  Alexander J. Leckey ,  Brendan Ryan ,  Patrick Fleming ,  Patrick Connor ,  David Hunt ,  Andrey Chilikin ,  Chris MacNamara

IPC: H04L12/863 ,  H04L12/935 ,  H04L12/861 ,  H04L12/801

Abstract: Technologies for reordering network packets on egress include a network interface controller (NIC) configured to associate a received network packet with a descriptor, generate a sequence identifier for the received network packet, and insert the generated sequence identifier into the associated descriptor. The NIC is further configured to determine whether the received network packet is to be transmitted from a compute device associated with the NIC to another compute device and insert, in response to a determination that the received network packet is to be transmitted to the another compute device, the descriptor into a transmission queue of descriptors. Additionally, the NIC is configured to transmit the network packet based on position of the descriptor in the transmission queue of descriptors based on the generated sequence identifier. Other embodiments are described herein.