公开(公告)号：US20160380629A1

公开(公告)日：2016-12-29

申请号：US14751060

申请日：2015-06-25

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H03K19/00 ,  H03K19/177

CPC classification number: H03K19/0008 ,  H03K19/17704 ,  H03K19/17744

Abstract: Described is an apparatus (e.g., a router) which comprises: multiple ports; and a plurality of crossbar circuits arranged such that at least one crossbar circuit receives all interconnects associated with a data bit of the multiple ports and is operable to re-route signals on those interconnects.

Abstract translation: 描述了一种装置（例如，路由器），其包括：多个端口; 以及布置成使得至少一个交叉电路接收与多个端口的数据位相关联的所有互连并且可操作以在那些互连上重新路由信号的多个交叉电路电路。

公开(公告)号：US20160182354A1

公开(公告)日：2016-06-23

申请号：US14579845

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Vivek K. De ,  Ram K. Krishnamurthy ,  Gregory K. Chen ,  Mark A. Anders ,  Himanshu Kaul

IPC: H04L12/727 ,  H04L12/26 ,  H04L12/933

CPC classification number: H04L45/121 ,  G06F15/7825 ,  H04L43/0852 ,  H04L45/125 ,  H04L45/24 ,  H04L45/60 ,  H04L49/109

Abstract: A router of a network-on-chip receives delay information associated with a plurality of links of the network-on-chip. The router determines at least one link of a data path based on the delay information.

Abstract translation: 片上网络的路由器接收与片上网络的多个链路相关联的延迟信息。 路由器基于延迟信息确定数据路径的至少一个链路。

公开(公告)号：US20160182256A1

公开(公告)日：2016-06-23

申请号：US14574189

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Mark A. Anders ,  Himanshu Kaul ,  Gregory K. Chen

IPC: H04L12/64 ,  H04L12/50 ,  H04L12/66 ,  H04L12/24

CPC classification number: H04L12/64 ,  G06F15/7825 ,  H04L12/50 ,  H04L12/6418 ,  H04L12/66 ,  H04L41/02 ,  H04L49/109 ,  Y02D10/12 ,  Y02D10/13

Abstract: A packet-switched request from a first router of a network-on-chip is received. The packet-switched request is generated by source logic of the network-on-chip. Circuit-switched data associated with the packet switched request is also received. The circuit-switched data is stored by a storage element. The circuit-switched data is sent towards destination logic identified in the packet-switched request.

Abstract translation: 接收来自片上网络的第一路由器的分组交换请求。 分组交换请求由片上网络的源逻辑产生。 还接收与分组交换请求相关联的电路交换数据。 电路交换数据由存储元件存储。 电路交换数据被发送到分组交换请求中标识的目的地逻辑。

公开(公告)号：US11790217B2

公开(公告)日：2023-10-17

申请号：US16583201

申请日：2019-09-25

Applicant: Intel Corporation

Inventor： Ram Krishnamurthy ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/063 ,  G06F7/523 ,  G06F9/38 ,  G06F9/30 ,  G06F7/509 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F7/5095 ,  G06F7/523 ,  G06F7/5443 ,  G06F9/30098 ,  G06F9/3893

Abstract: An apparatus is described. The apparatus includes a long short term memory (LSTM) circuit having a multiply accumulate circuit (MAC). The MAC circuit has circuitry to rely on a stored product term rather than explicitly perform a multiplication operation to determine the product term if an accumulation of differences between consecutive, preceding input values has not reached a threshold.

公开(公告)号：US11321263B2

公开(公告)日：2022-05-03

申请号：US14574352

申请日：2014-12-17

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Gregory K. Chen

IPC: H05K7/10 ,  G06F13/40 ,  H04L49/10 ,  H04L12/54

Abstract: An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

公开(公告)号：US11100385B2

公开(公告)日：2021-08-24

申请号：US15395758

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Gregory K. Chen ,  Huseyin E. Sumbul ,  Ram K. Krishnamurthy ,  Phil Knag

IPC: G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06F7/58

Abstract: Apparatus and method for a scalable, free running neuromorphic processor. For example, one embodiment of a neuromorphic processing apparatus comprises: a plurality of neurons; an interconnection network to communicatively couple at least a subset of the plurality of neurons; a spike controller to stochastically generate a trigger signal, the trigger signal to cause a selected neuron to perform a thresholding operation to determine whether to issue a spike signal.

公开(公告)号：US11062203B2

公开(公告)日：2021-07-13

申请号：US15394897

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Gregory K. Chen ,  Raghavan Kumar ,  Huseyin Ekin Sumbul ,  Phil Knag ,  Ram K. Krishnamurthy

IPC: G06N3/063 ,  G06N3/04

Abstract: In one embodiment, a method comprises receiving a selection of a neural network topology type; identifying a synapse memory mapping scheme for the selected neural network topology type from a plurality of synapse memory mapping schemes that are each associated with a respective neural network topology type; and mapping a plurality of synapse weights to locations in a memory based on the identified synapse memory mapping scheme.

公开(公告)号：US11048434B2

公开(公告)日：2021-06-29

申请号：US16147024

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Raghavan Kumar ,  Phil Knag ,  Gregory K. Chen ,  Huseyin Ekin Sumbul ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Abhishek Sharma ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/419 ,  G06F3/06 ,  G04F10/00 ,  G11C13/00 ,  G11C11/418 ,  G11C7/10 ,  G11C11/54

Abstract: A memory circuit has compute-in-memory (CIM) circuitry that performs computations based on time-to-digital conversion (TDC). The memory circuit includes an array of memory cells addressable with column address and row address. The memory circuit includes CIM sense circuitry to sense a voltage for multiple memory cells triggered together. The CIM sense circuitry including a TDC circuit to convert a time for discharge of the multiple memory cells to a digital value. A processing circuit determines a value of the multiple memory cells based on the digital value.

公开(公告)号：US10956813B2

公开(公告)日：2021-03-23

申请号：US16147109

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Ian A. Young ,  Ram Krishnamurthy ,  Sasikanth Manipatruni ,  Gregory K. Chen ,  Amrita Mathuriya ,  Abhishek Sharma ,  Raghavan Kumar ,  Phil Knag ,  Huseyin Ekin Sumbul

IPC: G06N3/06 ,  G06N3/063 ,  G11C11/419 ,  G11C5/06 ,  H03M7/30 ,  G11C11/413 ,  G11C7/10 ,  G11C11/54 ,  G06N3/04

Abstract: An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.

公开(公告)号：US20190205730A1

公开(公告)日：2019-07-04

申请号：US16299014

申请日：2019-03-11

Applicant: Intel Corporation

Inventor： Huseyin E. SUMBUL ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Christopher Knag ,  Ram Krishnamurthy

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: A neuromorphic computing system is provided which comprises: a synapse core; and a pre-synaptic neuron, a first post-synaptic neuron, and a second post-synaptic neuron coupled to the synaptic core, wherein the synapse core is to: receive a request from the pre-synaptic neuron, generate, in response to the request, a first address of the first post-synaptic neuron and a second address of the second post-synaptic neuron, wherein the first address and the second address are not stored in the synapse core prior to receiving the request.