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21.发明授权公开(公告)号：US10095573B2
公开(公告)日：2018-10-09
申请号：US15708079
申请日：2017-09-18
Applicant: Intel Corporation
Inventor： Tomer Stark , Ady Tal , Ron Gabor , Joseph Nuzman
Abstract: Memory corruption detection technologies are described. A processor can include a memory to store a memory corruption detection (MCD) table. A processor core of the processor can receive, from an application, an allocation request for an allocation of a memory object within a contiguous memory block in the memory. The processor core can allocate the contiguous memory block in view of a size of the memory object requested and write MCD meta-data into the MCD table, including a MCD identifier (ID) associated with the contiguous memory block and a MCD border value indicating a size of a memory region of the contiguous memory block.
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公开(公告)号：US09652375B2
公开(公告)日：2017-05-16
申请号：US14746702
申请日：2015-06-22
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman
CPC classification number: G06F12/023 , G06F11/0775 , G06F11/1004 , G06F11/1076 , G06F2212/1044
Abstract: Memory corruption detection technologies are described. An example processing system includes a processing core including a register to store an address of a memory corruption detection (MCD) table. The processing core can allocate a memory block of pre-determined size and can allocate a plurality of buffers within the memory block using a memory metadata word stored in an entry of the MCD table. The memory metadata word can include metadata that can identify a first bit range within the memory block for a first buffer and a second bit range within the memory block for a second buffer.
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23.发明申请公开(公告)号：US20160371179A1
公开(公告)日：2016-12-22
申请号：US14746702
申请日：2015-06-22
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Joseph Nuzman
IPC: G06F12/02
CPC classification number: G06F12/023 , G06F11/0775 , G06F11/1004 , G06F11/1076 , G06F2212/1044
Abstract: Memory corruption detection technologies are described. An example processing system includes a processing core including a register to store an address of a memory corruption detection (MCD) table. The processing core can allocate a memory block of pre-determined size and can allocate a plurality of buffers within the memory block using a memory metadata word stored in an entry of the MCD table. The memory metadata word can include metadata that can identify a first bit range within the memory block for a first buffer and a second bit range within the memory block for a second buffer
Abstract translation: 描述了内存损坏检测技术。 示例性处理系统包括处理核心，其包括用于存储存储器损坏检测（MCD）表的地址的寄存器。 处理核心可以分配预定大小的存储器块，并且可以使用存储在MCD表的条目中的存储器元数据字来在存储块内分配多个缓冲器。 存储器元数据字可以包括可识别第一缓冲器的存储器块内的第一位范围的元数据和用于第二缓冲器的存储器块内的第二位范围
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公开(公告)号：US09471494B2
公开(公告)日：2016-10-18
申请号：US14137432
申请日：2013-12-20
Applicant: Intel Corporation
Inventor： Rajesh M. Sankaran , Neil M. Schaper , Joseph Nuzman , Larisa Novakovsky , Yen-Cheng Liu , Gilbert Neiger , Raj K. Ramanujan
IPC: G06F12/08
CPC classification number: G06F12/0811 , G06F12/0804 , G06F12/0815 , G06F12/0831 , G06F2212/1032 , G06F2212/222
Abstract: An apparatus and method are described for performing a cache line write back operation. For example, one embodiment of a method comprises: initiating a cache line write back operation directed to a particular linear address; determining if a dirty cache line identified by the linear address exists at any cache of a cache hierarchy comprised of a plurality of cache levels; writing back the dirty cache line to memory if the dirty cache line exists in one of the caches; and responsively maintaining or placing the dirty cache line in an exclusive state in at least a first cache of the hierarchy.
Abstract translation: 描述了用于执行高速缓存行回写操作的装置和方法。 例如，方法的一个实施例包括：发起针对特定线性地址的高速缓存行回写操作; 确定由线性地址识别的脏高速缓存行是否存在于由多个高速缓存级别组成的高速缓存层级的任何高速缓存上; 如果脏缓存行存在于其中一个缓存中，则将脏缓存行写回内存; 以及响应地将所述脏高速缓存行维持或置于所述层次结构的至少第一高速缓存中的排他状态。
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公开(公告)号：US12111762B2
公开(公告)日：2024-10-08
申请号：US17130676
申请日：2020-12-22
Applicant: Intel Corporation
Inventor： Ayan Mandal , Leon Polishuk , Oz Shitrit , Joseph Nuzman
IPC: G06F3/06 , G06F12/0811 , G06F12/0815 , G06F12/128
CPC classification number: G06F12/0811 , G06F12/0815 , G06F12/128 , G06F2212/1032
Abstract: An embodiment of an integrated circuit may comprise a core, and a cache controller coupled to the core, the cache controller including circuitry to identify data from a working set for dynamic inclusion in a next level cache based on an amount of re-use of the next level cache, send a shared copy of the identified data to a requesting core of one or more processor cores, and maintain a copy of the identified data in the next level cache. Other embodiments are disclosed and claimed.
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Patent Agency Ranking
公开(公告)号：US20240296051A1
公开(公告)日：2024-09-05
申请号：US18661103
申请日：2024-05-10
Applicant: Intel Corporation
Inventor： Jason W. Brandt , Deepak K. Gupta , Rodrigo Branco , Joseph Nuzman , Robert S. Chappell , Sergiu Ghetie , Wojciech Powiertowski , Jared W. Stark, IV , Ariel Sabba , Scott J. Cape , Hisham Shafi , Lihu Rappoport , Yair Berger , Scott P. Bobholz , Gilad Holzstein , Sagar V. Dalvi , Yogesh Bijlani
CPC classification number: G06F9/3844 , G06F9/30101 , G06F9/3806
Abstract: Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.
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公开(公告)号：US10725755B2
公开(公告)日：2020-07-28
申请号：US15615798
申请日：2017-06-06
Applicant: Intel Corporation
Inventor： David J. Sager , Ruchira Sasanka , Ron Gabor , Shlomo Raikin , Joseph Nuzman , Leeor Peled , Jason A. Domer , Ho-Seop Kim , Youfeng Wu , Koichi Yamada , Tin-Fook Ngai , Howard H. Chen , Jayaram Bobba , Jeffrey J. Cook , Omar M. Shaikh , Suresh Srinivas
Abstract: Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program into multiple parallel threads are described. In some embodiments, the systems and apparatuses execute a method of original code decomposition and/or generated thread execution.
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公开(公告)号：US10521361B2
公开(公告)日：2019-12-31
申请号：US15904717
申请日：2018-02-26
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Ady Tal , Joseph Nuzman
Abstract: Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method receives, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory and sends, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.
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公开(公告)号：US20190205139A1
公开(公告)日：2019-07-04
申请号：US15858899
申请日：2017-12-29
Applicant: Intel Corporation
Inventor： Christopher J. Hughes , Joseph Nuzman , Jonas Svennebring , Doddaballapur N. Jayasimha , Samantika S. Sury , David A. Koufaty , Niall D. McDonnell , Yen-Cheng Liu , Stephen R. Van Doren , Stephen J. Robinson
IPC: G06F9/30
Abstract: Disclosed embodiments relate to spatial and temporal merging of remote atomic operations. In one example, a system includes an RAO instruction queue stored in a memory and having entries grouped by destination cache line, each entry to enqueue an RAO instruction including an opcode, a destination identifier, and source data, optimization circuitry to receive an incoming RAO instruction, scan the RAO instruction queue to detect a matching enqueued RAO instruction identifying a same destination cache line as the incoming RAO instruction, the optimization circuitry further to, responsive to no matching enqueued RAO instruction being detected, enqueue the incoming RAO instruction; and, responsive to a matching enqueued RAO instruction being detected, determine whether the incoming and matching RAO instructions have a same opcode to non-overlapping cache line elements, and, if so, spatially combine the incoming and matching RAO instructions by enqueuing both RAO instructions in a same group of cache line queue entries at different offsets.
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公开(公告)号：US20180181501A1
公开(公告)日：2018-06-28
申请号：US15904717
申请日：2018-02-26
Applicant: Intel Corporation
Inventor： Tomer Stark , Ron Gabor , Ady Tal , Joseph Nuzman
Abstract: Memory corruption detection technologies are described. A method may store in a register an address of a memory corruption detection (MCD) table. The method receives, from an application, a memory store request to store data in a first portion of a contiguous memory block of a memory and sends, to the application, a fault message when a fault event associated with the first portion occurs in view of a protection mode of the first portion, wherein the protection mode indicates that the first portion is write protected.
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