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    Dynamic detection and prediction for store-dependent branches
    22.
    发明授权
    Dynamic detection and prediction for store-dependent branches 有权

    公开(公告)号：US10430198B2

    公开(公告)日：2019-10-01

    申请号：US15870595

    申请日：2018-01-12

    Applicant: Intel Corporation

    Inventor： Saurabh Gupta ,  Rahul Pal ,  Niranjan Soundararajan ,  Ragavendra Natarajan ,  Sreenivas Subramoney

    IPC: G06F9/38

    Abstract: One embodiment provides an apparatus. The apparatus includes a store direct dependent (SDD) branch prediction circuitry and an SDD management circuitry. The store direct dependent (SDD) branch prediction circuitry is to store an SDD branch table. The SDD branch table is to store at least one record. Each record includes a branch instruction pointer (IP) field, a load IP field, a store IP field, a comparison info field and at least one of a store value field and/or a predicted outcome field. The SDD management circuitry is to populate the SDD branch table at runtime and to override a baseline branch prediction associated with an incoming branch IP with an SDD branch prediction, if the SDD branch table contains a first record populated with the incoming branch IP and at least one of a store value and/or an SDD predicted outcome.

    Branch predictor with empirical branch bias override
    23.
    发明授权
    Branch predictor with empirical branch bias override 有权

    公开(公告)号：US10423422B2

    公开(公告)日：2019-09-24

    申请号：US15383832

    申请日：2016-12-19

    Applicant: Intel Corporation

    Inventor： Niranjan K. Soundararajan ,  Sreenivas Subramoney ,  Rahul Pal ,  Ragavendra Natarajan

    IPC: G06F9/38

    Abstract: A processor may include a baseline branch predictor and an empirical branch bias override circuit. The baseline branch predictor may receive a branch instruction associated with a given address identifier, and generate, based on a global branch history, an initial prediction of a branch direction for the instruction. The empirical branch bias override circuit may determine, dependent on a direction of an observed branch direction bias in executed branch instruction instances associated with the address identifier, whether the initial prediction should be overridden, may determine, in response to determining that the initial prediction should be overridden, a final prediction that matches the observed branch direction bias, or may determine, in response determining that the initial prediction should not be overridden, a final prediction that matches the initial prediction. The predictor may update an entry in the global branch history reflecting the resolved branch direction for the instruction following its execution.

    CHANGING CACHE OWNERSHIP IN CLUSTERED MULTIPROCESSOR
    24.
    发明申请
    CHANGING CACHE OWNERSHIP IN CLUSTERED MULTIPROCESSOR 审中-公开

    公开(公告)号：US20170255553A1

    公开(公告)日：2017-09-07

    申请号：US15602603

    申请日：2017-05-23

    Applicant: INTEL CORPORATION

    Inventor： Rahul Pal ,  Ishwar Agarwal ,  Manoj K. Arora

    IPC: G06F12/084

    CPC classification number: G06F12/084 ,  G06F2212/2542 ,  G06F2212/271

    Abstract: A chip multiprocessor may include a first cluster and a second cluster, each having multiple cores of a processor, multiple co-located cache slices, and a memory controller. The processor stores directory information in a memory to indicate cluster cache ownership of a first address space to the first cluster. In response to a request to change the cluster cache ownership of the first address space to a second address space of the second cluster, the processor provides a quiesce period during which to block new read or write requests to the first cluster and the second cluster; drain read or write requests issued on the first cluster and the second cluster; and remove the block on new read or write requests. The processor may also update the directory information to change the cluster cache ownership of the first address space to the second address space of the second cluster.

    Method and apparatus for distributed snoop filtering
    25.
    发明授权
    Method and apparatus for distributed snoop filtering 有权

    公开(公告)号：US09727475B2

    公开(公告)日：2017-08-08

    申请号：US14497740

    申请日：2014-09-26

    Applicant: Intel Corporation

    Inventor： Rahul Pal ,  Ishwar Agarwal ,  Yen-Cheng Liu ,  Joseph Nuzman ,  Ashok Jagannathan ,  Bahaa Fahim ,  Nithiyanandan Bashyam

    IPC: G06F12/00 ,  G06F12/0875 ,  G06F12/0831

    CPC classification number: G06F12/0875 ,  G06F12/0831 ,  G06F2212/452

    Abstract: An apparatus and method are described for distributed snoop filtering. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions and process data; first snoop logic to track a first plurality of cache lines stored in a mid-level cache (“MLC”) accessible by one or more of the cores, the first snoop logic to allocate entries for cache lines stored in the MLC and to deallocate entries for cache lines evicted from the MLC, wherein at least some of the cache lines evicted from the MLC are retained in a level 1 (L1) cache; and second snoop logic to track a second plurality of cache lines stored in a non-inclusive last level cache (NI LLC), the second snoop logic to allocate entries in the NI LLC for cache lines evicted from the MLC and to deallocate entries for cache lines stored in the MLC, wherein the second snoop logic is to store and maintain a first set of core valid bits to identify cores containing copies of the cache lines stored in the NI LLC.

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