公开(公告)号：US10535601B2

公开(公告)日：2020-01-14

申请号：US16302692

申请日：2016-06-22

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr ,  Manish Chandhok

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/02 ,  H01L21/762 ,  H01L21/8234

Abstract: An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.

公开(公告)号：US10032857B2

公开(公告)日：2018-07-24

申请号：US15428087

申请日：2017-02-08

Applicant: Intel Corporation

Inventor： Ruth A. Brain

IPC: H05K1/00 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768

Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.

公开(公告)号：US09780038B2

公开(公告)日：2017-10-03

申请号：US15332199

申请日：2016-10-24

Applicant: Intel Corporation

Inventor： Ruth A. Brain ,  Kevin J. Fischer ,  Michael A. Childs

IPC: H01L23/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L21/311

CPC classification number: H01L23/5329 ,  H01L21/311 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76807 ,  H01L23/49827 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a dielectric layer on a contact point of an integrated circuit structure; forming a hardmask including a dielectric material on a surface of the dielectric layer; and forming at least one via in the dielectric layer to the contact point using the hardmask as a pattern. An apparatus including a circuit substrate including at least one active layer including a contact point; a dielectric layer on the at least one active layer; a hardmask including a dielectric material having a least one opening therein for an interconnect material; and an interconnect material in the at least one opening of the hardmask and through the dielectric layer to the contact point.

公开(公告)号：US20170148867A1

公开(公告)日：2017-05-25

申请号：US15428087

申请日：2017-02-08

Applicant: Intel Corporation

Inventor： Ruth A. Brain

IPC: H01L49/02 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L28/60 ,  G06F1/184 ,  H01L21/02148 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76877 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53228 ,  H01L23/5329 ,  H01L27/10805 ,  H01L27/10814 ,  H01L27/1085 ,  H01L27/10852 ,  H01L27/10885 ,  H01L28/40 ,  H01L28/90 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Capacitor structures for integrated circuit devices are provided. Capacitors include proximate dense or highly dense etchstop layers. The dense or highly dense etchstop layer is, for example, a high-k material. Capacitors are, for example, metal-insulator-metal (MIM) capacitors and are useful in DRAM (dynamic random access memory) and eDRAM (embedded dynamic random access memory) structures.