公开(公告)号：US10120686B2

公开(公告)日：2018-11-06

申请号：US15175899

申请日：2016-06-07

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Ching-Tsun Chou ,  Youfeng Wu

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: A processor includes a front end including circuitry to decode instructions from an instruction stream, a data cache unit including circuitry to cache data for the processor, and a binary translator. The binary translator includes circuitry to identify a redundant store in the instruction stream, mark the start and end of a region of the instruction stream with the redundant store, remove the redundant store, and store an amended instruction stream with the redundant store removed.

公开(公告)号：US20180285112A1

公开(公告)日：2018-10-04

申请号：US15474666

申请日：2017-03-30

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Jason M. Agron ,  Youfeng Wu

IPC: G06F9/30 ,  G06F12/0875 ,  G06F9/38

CPC classification number: G06F9/30174 ,  G06F9/30101 ,  G06F9/3842 ,  G06F9/467 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/507

Abstract: A processing device including a first shadow register, a second shadow register, and an instruction execution circuit, communicatively coupled to the first shadow register and the second shadow register, to receive a sequence of instructions comprising a first local commit marker, a first global commit marker, and a first register access instruction referencing an architectural register, speculatively execute the first register access instruction to generate a speculative register state value associated with a physical register, responsive to identifying the first local commit marker, store, in the first shadow register, the speculative register state value, and responsive to identifying the first global commit marker, store, in the second shadow register, the speculative register state value.

公开(公告)号：US09916164B2

公开(公告)日：2018-03-13

申请号：US14737058

申请日：2015-06-11

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Girish Venkatasubramanian ,  Howard H. Chen

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/45

CPC classification number: G06F9/3861 ,  G06F8/41 ,  G06F8/443 ,  G06F9/30058 ,  G06F9/3846

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed herein. An example apparatus includes an instruction profiler to identify a predicated block within instructions to be executed by a hardware processor. The example apparatus includes a performance monitor to access a mis-prediction statistic based on an instruction address associated with the predicated block. The example apparatus includes a region former to, in response to determining that the mis-prediction statistic is above a mis-prediction threshold, include the predicated block in a predicated region for optimization.