公开(公告)号：US20220320275A1

公开(公告)日：2022-10-06

申请号：US17848224

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Travis W. LAJOIE ,  Abhishek A. SHARMA ,  Juan ALZATE-VINASCO ,  Chieh-Jen KU ,  Shem OGADHOH ,  Allen B. GARDINER ,  Blake LIN ,  Yih WANG ,  Pei-Hua WANG ,  Jack T. KAVALIEROS ,  Bernhard SELL ,  Tahir GHANI

IPC: H01L29/06 ,  H01L27/12 ,  H01L27/105 ,  H01L21/02 ,  H01L29/423 ,  H01L21/764 ,  H01L21/768

Abstract: An integrated circuit includes a base, a first transistor structure on or above the base, and a second transistor structure on or above the base, where the second transistor structure is spaced from the first transistor structure. An insulator material at least partially encapsulates an airgap or other gas pocket laterally between the first transistor structure and the second transistor structure. The gas pocket is at least 5 nm in height and at least 5 nm wide according to an embodiment, and in some cases is as tall or taller than active device layers of the transistor structures it separates.

公开(公告)号：US20220029025A1

公开(公告)日：2022-01-27

申请号：US17496690

申请日：2021-10-07

Applicant: Intel Corporation

Inventor： Abhishek A. SHARMA ,  Van H. LE ,  Jack T. KAVALIEROS ,  Tahir GHANI ,  Yih WANG

IPC: H01L29/786 ,  H01L23/528 ,  H01L27/108 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49

Abstract: A thin-film transistor includes a gate electrode, a gate dielectric on the gate electrode, a first layer including a source region, a drain region, and a semiconductor region above and in direct contact with the gate dielectric and physically connecting the source and drain regions, and a second layer including an insulator material on the semiconductor region. The semiconductor region has less vertical thickness than the source and drain regions. In an embodiment, the thickness of the semiconductor region is no more than half that of the source and drain regions. In another embodiment, the second layer physically connects and electrically separates the source and drain regions. In yet another embodiment, a memory cell includes this transistor and a capacitor electrically connected to the drain region, the gate electrode being electrically connected to a wordline and the source region being electrically connected to a bitline.

公开(公告)号：US20190304978A1

公开(公告)日：2019-10-03

申请号：US15943537

申请日：2018-04-02

Applicant: Intel Corporation

Inventor： Yih WANG

IPC: H01L27/108

Abstract: Described herein are apparatuses, methods, and systems associated with a memory circuit in a three-dimensional (3D) integrated circuit (IC). A control circuit of the memory circuit may include logic transistors in a logic layer of the 3D IC. The control circuit may further include one or more interconnects (e.g., local or global interconnects) and/or other devices in one or more front-side metal layers of the 3D IC. The memory circuit may further include a memory array in back-side metal layers of the 3D IC. The memory array may be formed in the back-side metal layers that are closest to the logic layer. Other embodiments may be described and claimed.

公开(公告)号：US20190279697A1

公开(公告)日：2019-09-12

申请号：US16319239

申请日：2016-09-30

Applicant: INTEL CORPORATION

Inventor： Ilya KARPOV ,  Yih WANG ,  Fatih HAMZAOGLU ,  James CLARKE

IPC: G11C11/00 ,  H01L27/108 ,  H01L27/11514 ,  G11C11/22 ,  G11C11/407

Abstract: An apparatus is described. The apparatus includes a semiconductor chip that includes logic circuitry, embedded dynamic random access memory (DRAM) cells and embedded ferroelectric random access memory (FeRAM) cells.

公开(公告)号：US20180123038A1

公开(公告)日：2018-05-03

申请号：US15567575

申请日：2015-05-18

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Yih WANG ,  Elliot N. TAN

IPC: H01L45/00 ,  H01L27/108 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L27/24

CPC classification number: H01L45/1683 ,  G11C5/063 ,  G11C11/161 ,  H01L27/10814 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08

Abstract: Described is an apparatus which comprises: non-orthogonal transistor fins which are non-orthogonal to transistor gates; diffusion contacts with non-right angled sides, the diffusion contacts coupled to the non-orthogonal transistor fins; first vias; and at least one memory element coupled to at least one of the diffusion contacts through at least one of the first vias.