公开(公告)号：US20170250159A1

公开(公告)日：2017-08-31

申请号：US15503377

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Kevin J. LEE

IPC: H01L25/065 ,  H01L49/02 ,  H01L23/532 ,  H01L25/00 ,  H01L23/522 ,  H01L23/48

CPC classification number: H01L25/0652 ,  H01L23/145 ,  H01L23/481 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5228 ,  H01L23/525 ,  H01L23/53238 ,  H01L23/53252 ,  H01L25/50 ,  H01L28/40 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2924/15311

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US20190013354A1

公开(公告)日：2019-01-10

申请号：US16067803

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Yih WANG

IPC: H01L27/22 ,  H01L43/04 ,  H01L23/528 ,  H01L43/14 ,  H01L21/8234 ,  H01F41/34 ,  H01F10/32

Abstract: Damascene-based approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including a metallization layer. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall effect electrode (2T-1MTJ SHE electrode) bit cells. The spin hall effect electrodes of the 2T-1MTJ SHE electrode bit cells are disposed in a lower dielectric layer laterally adjacent to the metallization layer of the logic region. The MTJs of the 2T-1MTJ SHE electrode bit cells are disposed in an upper dielectric layer laterally adjacent to the metallization layer of the logic region.

公开(公告)号：US20200227472A1

公开(公告)日：2020-07-16

申请号：US16831658

申请日：2020-03-26

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Tahir GHANI ,  Joseph M. STEIGERWALD ,  John H. EPPLE ,  Yih WANG

IPC: H01L27/22 ,  H01L43/12 ,  H01L43/08 ,  G11C11/16

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.

公开(公告)号：US20190013353A1

公开(公告)日：2019-01-10

申请号：US16067801

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Oleg GOLONZKA ,  Tahir GHANI ,  Ruth A. BRAIN ,  Yih WANG

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L23/532 ,  G11C11/16 ,  H01L23/522

Abstract: Approaches for integrating spin torque transfer magnetic random access memory (STT-MRAM) memory arrays into a logic processor, and the resulting structures, are described. In an example, a logic processor including a logic region including metal line/via pairings disposed in a dielectric layer disposed above a substrate. The logic processor also includes a spin torque transfer magnetoresistive random access memory (STT-MRAM) array including a plurality of magnetic tunnel junctions (MTJs). The MTJs are disposed in the dielectric layer.

公开(公告)号：US20190109107A1

公开(公告)日：2019-04-11

申请号：US16216881

申请日：2018-12-11

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Ruchir SARASWAT ,  Uwe ZILLMANN ,  Nicholas P. COWLEY ,  Richard J. GOLDMAN

IPC: H01L23/00 ,  H01L23/64 ,  H01L23/48 ,  H01L23/522 ,  H01L23/66 ,  H01F27/28 ,  G06F1/16 ,  H03H7/42 ,  H03H9/64

Abstract: Described is an apparatus which comprises: a backside of a first die having a redistribution layer (RDL); and one or more passive planar devices disposed on the backside, the one or more passive planar devices formed in the RDL.

公开(公告)号：US20180123038A1

公开(公告)日：2018-05-03

申请号：US15567575

申请日：2015-05-18

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Yih WANG ,  Elliot N. TAN

IPC: H01L45/00 ,  H01L27/108 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  H01L27/24

CPC classification number: H01L45/1683 ,  G11C5/063 ,  G11C11/161 ,  H01L27/10814 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L43/08 ,  H01L43/12 ,  H01L45/06 ,  H01L45/08

Abstract: Described is an apparatus which comprises: non-orthogonal transistor fins which are non-orthogonal to transistor gates; diffusion contacts with non-right angled sides, the diffusion contacts coupled to the non-orthogonal transistor fins; first vias; and at least one memory element coupled to at least one of the diffusion contacts through at least one of the first vias.

公开(公告)号：US20190198481A1

公开(公告)日：2019-06-27

申请号：US16287915

申请日：2019-02-27

Applicant: Intel Corporation

Inventor： Kevin J. LEE

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/522 ,  H01L49/02 ,  H01L25/00 ,  H01L23/532

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) die. In embodiments, the IC die may include a semiconductor substrate, a plurality of active components disposed on a first side of the semiconductor substrate, and a plurality of passive components disposed on a second side of the semiconductor substrate. In embodiments the second side may be disposed opposite the first side. The passive components may, in some embodiments, include capacitors and/or resistors while the active components may, in some embodiments, include transistors. Other embodiments may be described and/or claimed.

公开(公告)号：US20190006416A1

公开(公告)日：2019-01-03

申请号：US16067800

申请日：2016-03-07

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Yih WANG

IPC: H01L27/22 ,  H01L43/06 ,  H01L43/04 ,  H01L43/10 ,  H01L43/14 ,  G11C11/16 ,  G11C11/18

Abstract: Approaches for embedding spin hall MTJ devices into a logic processor, and the resulting structures, are described. In an example, a logic processor includes a logic region including fm-FET transistors disposed in a dielectric layer disposed above a substrate. The logic processor also includes a memory array including a plurality of two-transistor one magnetic tunnel junction (MTJ) spin hall electrode (2T1MTJ SHE) bit cells. The transistors of the 2T1MTJ SHE bit cells are fm-FET transistors disposed in the dielectric layer.

公开(公告)号：US20180277593A1

公开(公告)日：2018-09-27

申请号：US15959027

申请日：2018-04-20

Applicant: Intel Corporation

Inventor： Kevin J. LEE ,  Tahir GHANI ,  Joseph M. STEIGERWALD ,  John H. EPPLE ,  Yih WANG

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/08 ,  H01L43/12 ,  H05K999/99

Abstract: An embodiment integrates memory, such as spin-torque transfer magnetoresistive random access memory (STT-M RAM) within a logic chip. The STT-MRAM includes a magnetic tunnel junction (MTJ) that has an upper MTJ layer, a lower MTJ layer, and a tunnel barrier directly contacting the upper MTJ layer and the lower MTJ layer; wherein the upper MTJ layer includes an upper MTJ layer sidewall and the lower MTJ layer includes a lower MTJ sidewall horizontally offset from the upper MTJ layer. Another embodiment includes a memory area, comprising a MTJ, and a logic area located on a substrate; wherein a horizontal plane intersects the MTJ, a first Inter-Layer Dielectric (ILD) material adjacent the MTJ, and a second ILD material included in the logic area, the first and second ILD materials being unequal to one another. Other embodiments are described herein.