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    OPTIMIZATING SEMICONDUCTOR BINNING BY FEED-FORWARD PROCESS ADJUSTMENT
    24.
    发明申请
    OPTIMIZATING SEMICONDUCTOR BINNING BY FEED-FORWARD PROCESS ADJUSTMENT 有权

    公开(公告)号：US20210249288A1

    公开(公告)日：2021-08-12

    申请号：US17244084

    申请日：2021-04-29

    Applicant: International Business Machines Corporation

    Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert ,  James Stathis

    IPC: H01L21/67 ,  G06N5/04 ,  G06N20/00

    Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target sorting bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

    Optimizing semiconductor binning by feed-forward process adjustment
    25.
    发明授权
    Optimizing semiconductor binning by feed-forward process adjustment 有权

    公开(公告)号：US11049744B2

    公开(公告)日：2021-06-29

    申请号：US15791451

    申请日：2017-10-24

    Applicant: International Business Machines Corporation

    Inventor： Benjamin D. Briggs ,  Lawrence A. Clevenger ,  Nicholas A. Lanzillo ,  Michael Rizzolo ,  Theodorus E. Standaert ,  James Stathis

    IPC: H01L21/67 ,  G06N20/00 ,  G06N5/04

    Abstract: One or more processors determine a predicted sorting bin of a semiconductor device, based on measurement and test data performed on the semiconductor device subsequent to a current metallization layer. A current predicted sorting bin and a target soring bin are determined by a machine learning model for the semiconductor device; the target bin include higher performance semiconductor devices than the predicted sorting bin. The model determines a performance level improvement attainable by adjustments made to process parameters of subsequent metallization layers of the semiconductor device. Adjustments to process parameters are generated, based on measurement and test data of the current metallization layer of semiconductor device, and the adjustment outputs for the process parameters of the subsequent metallization layers of the semiconductor device are made available to the one or more subsequent metallization layer processes by a feed-forward mechanism.

    FULLY ALIGNED SEMICONDUCTOR DEVICE WITH A SKIP-LEVEL VIA
    28.
    发明申请
    FULLY ALIGNED SEMICONDUCTOR DEVICE WITH A SKIP-LEVEL VIA 审中-公开

    公开(公告)号：US20200136028A1

    公开(公告)日：2020-04-30

    申请号：US16596152

    申请日：2019-10-08

    Applicant: International Business Machines Corporation

    Inventor： Nicholas A. Lanzillo ,  Benjamin D. Briggs ,  Chih-Chao Yang ,  Hsueh-Chung Chen ,  Lawrence A. Clevenger

    IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

    Abstract: A semiconductor structure includes a memory element disposed on a first metal layer. A first cap layer is disposed on the first metal layer and sidewalls of the memory element. A first dielectric layer is disposed on a top surface of the first cap layer on the first metal layer and a portion of the first cap layer on the sidewalls of the memory element. A second metal layer is disposed on the first dielectric layer and sidewalls of the first cap layer. A second cap layer is disposed on a top surface of the second metal layer. A second dielectric layer is disposed on the second cap layer. A via is in the second dielectric layer and exposes a top surface of the memory element. A third metal layer is disposed on the second dielectric layer and in the via.

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