Time division multiplexed limited switch dynamic logic
    22.
    发明授权
    Time division multiplexed limited switch dynamic logic 有权
    时分复用有限开关动态逻辑

    公开(公告)号:US09030234B2

    公开(公告)日:2015-05-12

    申请号:US13937396

    申请日:2013-07-09

    IPC分类号: H03K19/096

    CPC分类号: H03K19/0963 H03K19/096

    摘要: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

    摘要翻译: 有限开关动态逻辑(LSDL)电路包括动态逻辑电路和静态逻辑电路。 动态逻辑电路包括预充电装置,其被配置为在第一评估时钟信号和第二评估时钟信号的预充电阶段期间预充电动态节点。 第一评估树被配置为在第一评估时钟信号的评估阶段期间响应于一个或多个第一输入信号来评估动态节点为第一逻辑值。 第二评估树被配置为在第二评估时钟信号的评估阶段期间响应于一个或多个第二输入信号将动态节点评估为第二逻辑值。 静态逻辑电路被配置为根据输出锁存时钟信号响应于动态节点提供LSDL电路的输出。

    Shared bit line SMT MRAM array with shunting transistors between bit lines
    23.
    发明授权
    Shared bit line SMT MRAM array with shunting transistors between bit lines 有权
    共享位线SMT MRAM阵列,在位线之间分流晶体管

    公开(公告)号:US08654577B2

    公开(公告)日:2014-02-18

    申请号:US13887291

    申请日:2013-05-04

    IPC分类号: G11C11/00

    摘要: An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

    摘要翻译: SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。 列的每个SMT MRAM单元连接到真数据位线,并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。 分流开关装置连接在每个真实数据位线和共享补码数据位线之间,用于选择性地将一条真实数据位线连接到共享补码数据位线,以有效地减小补码数据位线的电阻, 以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

    TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC
    24.
    发明申请
    TIME DIVISION MULTIPLEXED LIMITED SWITCH DYNAMIC LOGIC 有权
    时分多路复用有限公司开关动态逻辑

    公开(公告)号:US20130328593A1

    公开(公告)日:2013-12-12

    申请号:US13937396

    申请日:2013-07-09

    IPC分类号: H03K19/096

    CPC分类号: H03K19/0963 H03K19/096

    摘要: A limited switch dynamic logic (LSDL) circuit includes a dynamic logic circuit and a static logic circuit. The dynamic logic circuit includes a precharge device configured to precharge a dynamic node during a precharge phase of a first evaluation clock signal and a second evaluation clock signal. A first evaluation tree is configured to evaluate the dynamic node to a first logic value in response to one or more first input signals during an evaluation phase of the first evaluation clock signal. A second evaluation tree is configured to evaluate the dynamic node to a second logic value in response to one or more second input signals during an evaluation phase of the second evaluation clock signal. A static logic circuit is configured to provide an output of the LSDL circuit in response to the dynamic node according to an output latch clock signal.

    摘要翻译: 有限开关动态逻辑(LSDL)电路包括动态逻辑电路和静态逻辑电路。 动态逻辑电路包括预充电装置,其被配置为在第一评估时钟信号和第二评估时钟信号的预充电阶段期间预充电动态节点。 第一评估树被配置为在第一评估时钟信号的评估阶段期间响应于一个或多个第一输入信号来评估动态节点为第一逻辑值。 第二评估树被配置为在第二评估时钟信号的评估阶段期间响应于一个或多个第二输入信号将动态节点评估为第二逻辑值。 静态逻辑电路被配置为根据输出锁存时钟信号响应于动态节点提供LSDL电路的输出。

    Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

    公开(公告)号:US11687148B1

    公开(公告)日:2023-06-27

    申请号:US17729638

    申请日:2022-04-26

    IPC分类号: G06F1/00 G06F1/3296 G06F1/324

    CPC分类号: G06F1/3296 G06F1/324

    摘要: A system and method for supporting an interconnection of processor cores, each core with functional state monitors for monitoring operations of each processor core, the processor cores interconnected using a resistive network connected between two-terminal regions being embedded in the resistive network such that each terminal of a region may be connected by controllable resistors to one or both fixed rails or by controllable resistors to one or more intermediate nodes. The resistor values are configurable to provide indirect control of the voltages across each two-terminal region, allowing full dynamic control of voltages of the two-terminal regions in a range up to the full voltage between the two voltage rails, and where a management unit accesses the functional state monitors and controls the resistor values. Feedback from functional state monitors allow the operating frequency to extend down to arbitrarily low values and up to the limits imposed by the technology.

    Two-stage gated-diode sense amplifier

    公开(公告)号:US10930325B2

    公开(公告)日:2021-02-23

    申请号:US16257562

    申请日:2019-01-25

    发明人: Yutaka Nakamura

    摘要: A two-stage gated-diode sense amplifier includes a first transistor connected to an input node, a second transistor connected to a boost node, the input node and a setting line, a first inverter including a third transistor connected to a power supply voltage (VDD), a first output corresponding to the first inverter and the setting line, and a fourth transistor connected to ground, the first output and the setting line, a fifth transistor connected to the first output, the first transistor and the boost node, and a second associated with a second output corresponding to the second inverter, the second inverter including a sixth transistor connected to VDD, the second output and the first output, and a seventh transistor connected to ground, the second output and the first output.