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    SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BIT LINES
    2.
    发明申请
    SHARED BIT LINE SMT MRAM ARRAY WITH SHUNTING TRANSISTORS BETWEEN BIT LINES 有权
    共享位线SMT MRAM阵列与位线之间的分束晶体管

    公开(公告)号：US20130265821A1

    公开(公告)日：2013-10-10

    申请号：US13887289

    申请日：2013-05-04

    申请人： International Business Machines Corporation ,  MagIC Technologies, Inc.

    发明人： Hsu-Kai Yang ,  Yutaka Nakamura ,  John Debrosse

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1653 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1675

    摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

    摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。 列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。 分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻， 以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

    Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines
    4.
    发明申请
    Shared Bit Line SMT MRAM Array with Shunting Transistors Between Bit Lines 有权
    共享位线SMT MRAM阵列与位线之间的分流晶体管

    公开(公告)号：US20130301347A1

    公开(公告)日：2013-11-14

    申请号：US13887291

    申请日：2013-05-04

    申请人： MagIC Technologies, Inc. ,  International Business Machines Corporation

    发明人： Hsu-Kai Yang ,  Yutaka Nakamura ,  John Debrosse

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1653 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1675

    摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

    摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。 列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。 分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻， 以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

    Shared bit line SMT MRAM array with shunting transistors between bit lines
    5.
    发明授权
    Shared bit line SMT MRAM array with shunting transistors between bit lines 有权
    共享位线SMT MRAM阵列，在位线之间分流晶体管

    公开(公告)号：US08570793B1

    公开(公告)日：2013-10-29

    申请号：US13887289

    申请日：2013-05-04

    申请人： MagIC Technologies, Inc. ,  International Business Machines Corporation

    发明人： Hsu-Kai Yang ,  Yutaka Nakamura ,  John Debrosse

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1653 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1675

    摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

    摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。 列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。 分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻， 以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

    Shared bit line SMT MRAM array with shunting transistors between bit lines
    6.
    发明授权
    Shared bit line SMT MRAM array with shunting transistors between bit lines 有权
    共享位线SMT MRAM阵列，在位线之间分流晶体管

    公开(公告)号：US08654577B2

    公开(公告)日：2014-02-18

    申请号：US13887291

    申请日：2013-05-04

    申请人： MagIC Technologies, Inc. ,  International Business Machines Corporation

    发明人： Hsu-Kai Yang ,  Yutaka Nakamura ,  John Debrosse

    IPC分类号： G11C11/00

    CPC分类号： G11C11/1653 ,  G11C7/18 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1675

    摘要： An array of rows and columns of SMT MRAM cells has each of the columns associated with one of its adjacent columns. Each of the SMT MRAM cells of the column is connected to a true data bit line and each of the SMT MRAM cells of the associated pair of columns is connected to a shared complement data bit line. A shunting switch device is connected between each of the true data bit lines and the shared complement data bit line for selectively connecting one of the true data bit lines to the shared complement data bit line to effectively reduce the resistance of the complement data bit line and to eliminate program disturb effects in adjacent non-selected columns of the SMT MRAM cells.

    摘要翻译： SMT MRAM单元格的行和列阵列具有与其相邻列之一相关联的每个列。 列的每个SMT MRAM单元连接到真数据位线，并且相关联的列对的每个SMT MRAM单元连接到共享补码数据位线。 分流开关装置连接在每个真实数据位线和共享补码数据位线之间，用于选择性地将一条真实数据位线连接到共享补码数据位线，以有效地减小补码数据位线的电阻， 以消除SMT MRAM单元的相邻非选择列中的程序干扰效应。

    Cascode complimentary dual level shifter
    9.
    发明授权
    Cascode complimentary dual level shifter 有权

    公开(公告)号：US10115450B1

    公开(公告)日：2018-10-30

    申请号：US15617020

    申请日：2017-06-08

    申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

    发明人： John K. DeBrosse ,  Yutaka Nakamura

    IPC分类号： G11C5/14 ,  G11C11/408 ,  H03K3/356

    摘要： A level shifter and dynamic random-access memory that includes a first output terminal and a second output terminal. A first voltage or a third voltage is outputted from the first output terminal. A second voltage or a fourth voltage is outputted from the second output terminal. The second voltage is lower than the first voltage. The third voltage is lower than the first voltage and higher than the second voltage. The fourth voltage is lower than the first voltage and higher than the third voltage.