公开(公告)号：US20140251517A1

公开(公告)日：2014-09-11

申请号：US14281260

申请日：2014-05-19

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： B60B9/04

CPC分类号： B60B9/04 ,  B60B9/26

摘要： An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

摘要翻译： 具有成对辐条环的互锁的可压缩辐条轮系统。 将左右轮辐锁定成对可以提供改善的载荷下的轮胎位移。 由左侧辐条和右辐条组成的左右半轮。 使得轮缘或轮胎的新型安装系统能够附接到辐条系统。

公开(公告)号：US08757228B2

公开(公告)日：2014-06-24

申请号：US13074394

申请日：2011-03-29

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： B60B9/02

CPC分类号： B60B9/04 ,  B60B9/26

摘要： An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

摘要翻译： 具有成对辐条环的互锁的可压缩辐条轮系统。 将左右轮辐锁定成对可以提供改善的载荷下的轮胎位移。 由左侧辐条和右辐条组成的左右半轮。 使得轮缘或轮胎的新型安装系统能够附接到辐条系统。

公开(公告)号：US20110240189A1

公开(公告)日：2011-10-06

申请号：US13074394

申请日：2011-03-29

申请人： Drew J. Dutton

发明人： Drew J. Dutton

IPC分类号： B60B9/02

CPC分类号： B60B9/04 ,  B60B9/26

摘要： An interlocking, compressible spoke wheel system having a ring of paired spokes. The locking of left and right spokes into pairs provides improved tire displacement under loads. The left and right half wheels formed by sets of left spokes and right spokes. enable a novel mounting system for the wheel rim or tire to attach to the spoke system.

摘要翻译： 具有成对辐条环的互锁的可压缩辐条轮系统。 将左右轮辐锁定成对可以提供改善的载荷下的轮胎位移。 由左侧辐条和右辐条组成的左右半轮。 使得轮缘或轮胎的新型安装系统能够附接到辐条系统。

公开(公告)号：US07917741B2

公开(公告)日：2011-03-29

申请号：US11733599

申请日：2007-04-10

申请人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

发明人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F1/24 ,  G06F21/00 ,  G06F12/14 ,  G06F7/04 ,  G06F17/30 ,  G08B29/00

CPC分类号： G06F21/575

摘要： System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.

摘要翻译： 用于在包括主处理器和存储器的系统中执行预引导安全验证的系统和方法，具有辅助存储器的嵌入式微控制器，例如片上ROM或被控制以禁止用户篡改内容的内存的存储器 存储器以及耦合到嵌入式微控制器的一个或多个预引导安全组件。 上电后，但在主机处理器启动之前，嵌入式微控制器访问辅助存储器并执行程序指令，以使用一个或多个预引导安全组件来验证系统的安全性。 一个或多个预引导安全组件包括至少一个身份验证组件，例如智能卡或生物测定传感器，例如指纹传感器，视网膜扫描器和/或声纹印刷传感器等，和/ 或至少一个系统验证组件（例如TPM）来查询系统的系统状态信息，并验证系统是否未被泄露。

公开(公告)号：US20090327678A1

公开(公告)日：2009-12-31

申请号：US11733599

申请日：2007-04-10

申请人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

发明人： Drew J. Dutton ,  Alan D. Berenbaum ,  Richard E. Wahler ,  Raphael Weiss

IPC分类号： G06F15/177

CPC分类号： G06F21/575

摘要： System and method for performing pre-boot security verification in a system that includes a host processor and memory, an embedded microcontroller with an auxiliary memory, e.g., an on-chip ROM, or memory controlled to prohibit user-tampering with the contents of the memory, and one or more pre-boot security components coupled to the embedded microcontroller. Upon power-up, but before host processor boot-up, the embedded microcontroller accesses the auxiliary memory and executes the program instructions to verify system security using the one or more pre-boot security components. The one or more pre-boot security components includes at least one identity verification component, e.g., a smart card, or a biometric sensor, e.g., a fingerprint sensor, a retinal scanner, and/or a voiceprint sensor, etc., and/or at least one system verification component, e.g., TPM, to query the system for system state information, and verify that the system has not been compromised.

摘要翻译： 用于在包括主处理器和存储器的系统中执行预引导安全验证的系统和方法，具有辅助存储器的嵌入式微控制器，例如片上ROM或被控制以禁止用户篡改内容的内存的存储器 存储器以及耦合到嵌入式微控制器的一个或多个预引导安全组件。 上电后，但在主机处理器启动之前，嵌入式微控制器访问辅助存储器并执行程序指令，以使用一个或多个预引导安全组件来验证系统的安全性。 一个或多个预引导安全组件包括至少一个身份验证组件，例如智能卡或生物测定传感器，例如指纹传感器，视网膜扫描器和/或声纹印刷传感器等，和/ 或至少一个系统验证组件（例如TPM）来查询系统的系统状态信息，并验证系统是否未被泄露。

公开(公告)号：US06061756A

公开(公告)日：2000-05-09

申请号：US89025

申请日：1998-06-02

申请人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

发明人： Drew J. Dutton ,  Scott E. Swanstrom ,  J. Andrew Lambrecht

IPC分类号： G06F13/368 ,  G06F13/372 ,  G06F13/40 ,  H04N21/238 ,  G06F13/38

CPC分类号： H04N21/238 ,  G06F13/368 ,  G06F13/372 ,  G06F13/4013 ,  G06F13/4027

摘要： A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local system bus or expansion bus, such as the PCI bus, and may also include a dedicated real-time bus or multimedia bus. Various multimedia devices are coupled to one or more of the expansion bus and/or the multimedia bus. The computer system includes byte slicing and/or data packing logic coupled to one or more of the expansion bus and/or the multimedia bus which operates to allow different data streams to use different byte channels simultaneously. Thus the byte sliced bus allows different peripherals to share the bus simultaneously. The byte slicing logic thus may assign one data stream to a subset of the total byte lanes on the multimedia bus, and fill the unused byte lanes with another data stream. The data packing logic may optimally fill the bus with data having more or fewer bits than the bus. The computer system of the present invention thus provides much greater performance for real-time applications than prior systems.

摘要翻译： 针对实时应用程序进行了优化的计算机系统，提高了当前计算机体系结构的性能。 该系统包括标准本地系统总线或扩展总线，例如PCI总线，并且还可以包括专用实时总线或多媒体总线。 各种多媒体设备耦合到一个或多个扩展总线和/或多媒体总线。 计算机系统包括耦合到扩展总线和/或多媒体总线中的一个或多个的字节分片和/或数据打包逻辑，其操作以允许不同的数据流同时使用不同的字节通道。 因此，字节分片总线允许不同的外设同时共享总线。 因此，字节分片逻辑可以将一个数据流分配给多媒体总线上的总字节通道的子集，并且用另一个数据流填充未使用的字节通道。 数据打包逻辑可以使用比总线更多或更少位的数据来最佳地填充总线。 因此，本发明的计算机系统为实时应用提供比现有系统更大的性能。

公开(公告)号：US5822778A

公开(公告)日：1998-10-13

申请号：US886421

申请日：1997-07-01

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/02

CPC分类号： G06F9/30138 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30185 ,  G06F9/342 ,  G06F9/3844

摘要： A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to control the selection of a bank of registers to use for the instruction operands. Each bank of registers includes the full complement of AMD 80x86 Series registers. Additional registers are available to a program other than the AMD 80x86 Series architecture specifies, but the instruction encoding is unchanged. Having more registers available to a program allows for more operands to be stored in the registers. Since registers are accessible in a shorter period of time than memory, operand access time is decreased.

摘要翻译： 提供了微处理器，其被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段超越前缀，并且使用前缀值或存储在相关联的段寄存器中的值来控制寄存器组的选择 用于指令操作数。 每个寄存器组包括AMD + Z 80x86系列寄存器的全套。 除AMD + Z 80x86系列架构外，其他寄存器可用于指定，但指令编码不变。 有更多的寄存器可用于程序允许更多的操作数存储在寄存器中。 由于寄存器在比内存更短的时间段内可访问，所以操作数访问时间减少。

公开(公告)号：US5768574A

公开(公告)日：1998-06-16

申请号：US914698

申请日：1997-08-19

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30094 ,  G06F9/30185 ,  G06F9/34 ,  G06F9/3844

摘要： A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to selectively enable condition flag modification for instructions. An instruction which modifies the condition flags and a branch instruction intended to branch based on the condition flags set by the instruction may be separated by numerous instructions which do not modify the condition flags. When the branch instruction is decoded, the condition flags it depends on may already be available. In another embodiment of the present microprocessor, the segment register override bytes are used to select between multiple sets of condition flags. Multiple conditions may be retained by the microprocessor for later examination. Conditions which a program utilizes multiple times in a program may be maintained while other conditions may be generated and utilized.

摘要翻译： 提供了微处理器，其被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段超越前缀，并且使用前缀值或存储在相关联的段寄存器中的值来选择性地启用用于指令的条件标志修改。 根据指令设定的条件标志修改条件标志和分支指令的指令可以被不修改条件标志的许多指令分开。 当分支指令被解码时，它所依赖的条件标志可能已经可用。 在本微处理器的另一实施例中，段寄存器覆盖字节用于在多组条件标志之间进行选择。 微处理器可以保留多个条件供以后检查。 在程序中利用多次的程序的条件可以被保持，而可以产生和利用其他条件。

公开(公告)号：US5761452A

公开(公告)日：1998-06-02

申请号：US617413

申请日：1996-03-18

申请人： Douglas A. Hooks ,  Drew J. Dutton

发明人： Douglas A. Hooks ,  Drew J. Dutton

IPC分类号： G06F13/364 ,  G06F13/00

CPC分类号： G06F13/364

摘要： An improved bus arbitration system comprising an information bus, first and second bus masters connected to the bus and a bus arbiter for controlling ownership of the bus. The first bus master is adapted to perform speculative pre-fetching and has a first REQ signal for requesting ownership of the bus and an SP signal for indicating when a bus ownership request is for a speculative pre-fetch. The second bus master has a second REQ signal for requesting ownership of the bus. The bus arbiter is configured such that when the first bus master asserts its REQ signal and its SP signal and the second bus master asserts its REQ signal, the bus arbiter assigns higher priority to the second bus master in response to the SP signal.

摘要翻译： 一种改进的总线仲裁系统，包括信息总线，连接到总线的第一和第二总线主机以及用于控制总线所有权的总线仲裁器。 第一总线主机适于执行推测性预取，并且具有用于请求总线所有权的第一REQ信号和用于指示总线所有权请求何时用于推测性预取的SP信号。 第二总线主机具有用于请求所有者总线的第二REQ信号。 总线仲裁器被配置为使得当第一总线主机断言其REQ信号及其SP信号，并且第二总线主机断言其REQ信号时，总线仲裁器响应于SP信号为第二总线主机分配更高的优先级。

公开(公告)号：US5754190A

公开(公告)日：1998-05-19

申请号：US481630

申请日：1995-06-07

申请人： Drew J. Dutton ,  Douglas D. Gephardt ,  Steven L. Belt ,  Brett B. Stewart ,  Rita M. Wisor

发明人： Drew J. Dutton ,  Douglas D. Gephardt ,  Steven L. Belt ,  Brett B. Stewart ,  Rita M. Wisor

IPC分类号： G06T9/00 ,  G06T13/00

CPC分类号： G06T9/001

摘要： A method and apparatus for transferring original data which includes images, between two stations located a distance apart, without actual transmission of the image portion of the data. A library of images are provided at each of the stations. The image to be transferred is processed into a description of the image which allows the reproduction of the image at the receiving end of the transmission using the images contained in the image library in the receiving station.

摘要翻译： 一种用于传送原始数据的方法和装置，其中包括位于距离分开的两个站之间的图像，而不实际传输数据的图像部分。 每个电台都提供图像库。 要传送的图像被处理成图像的描述，其允许使用包含在接收站中的图像库中的图像在传输的接收端再现图像。