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    INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS
    21.
    发明申请
    INPUT BUFFER CIRCUIT OF SEMICONDUCTOR APPARATUS 有权
    半导体器件的输入缓冲电路

    公开(公告)号：US20100039142A1

    公开(公告)日：2010-02-18

    申请号：US12540496

    申请日：2009-08-13

    申请人： JI WANG LEE ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Jae Min Jang ,  Chang Kun Park

    发明人： JI WANG LEE ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Jae Min Jang ,  Chang Kun Park

    IPC分类号： H03K5/153

    CPC分类号： H03K5/153

    摘要： The input buffer circuit of a semiconductor apparatus includes a first buffering unit that that is activated by a voltage level difference between a first voltage terminal and a second voltage terminal, and generates a first compare signal and a second compare signal by comparing the voltage levels of reference voltage and an input signal; a control unit that controls the amount of current flowing between the second voltage terminal and a ground terminal by comparing the voltage levels of the reference voltage and the second compare signal; and a second buffering unit that generates an output signal by comparing the voltage levels of the input signal and the first compare signal.

    摘要翻译： 半导体装置的输入缓冲电路包括第一缓冲单元，其由第一电压端子和第二电压端子之间的电压电平差激活，并且通过比较第一电压电平和第二电压电平的电压电平来生成第一比较信号和第二比较信号 参考电压和输入信号; 控制单元，其通过比较所述参考电压和所述第二比较信号的电压电平来控制在所述第二电压端子和接地端子之间流动的电流量; 以及第二缓冲单元，其通过比较输入信号和第一比较信号的电压电平来产生输出信号。

    DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME
    23.
    发明申请
    DUTY CYCLE CORRECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS INCLUDING THE SAME 有权
    占空比校正电路和半导体集成电路设备，包括它们

    公开(公告)号：US20090231006A1

    公开(公告)日：2009-09-17

    申请号：US12331294

    申请日：2008-12-09

    申请人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

    发明人： Jae Min Jang ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Chang Kun Park

    IPC分类号： H03K5/04

    CPC分类号： H03K5/1565 ,  H03K5/151 ,  H03K2005/00058

    摘要： A duty cycle correction circuit includes a phase splitter configured to control a phase of a DLL clock signal to generate a rising clock signal and a falling clock signal, a clock delay unit configured to delay the rising clock signal and the falling clock signal in response to control signals to generate a delayed rising clock signal and a delayed falling clock signal, a duty ratio correction unit configured to generate a correction rising clock signal and a correction falling clock signal that toggle in response to an edge timing of the delayed rising clock signal and the delayed falling clock signal, and a delay control unit configured to detect duty cycles of the correction rising clock signal and the correction falling clock signal to generate the control signals.

    摘要翻译： 占空比校正电路包括：相位分离器，被配置为控制DLL时钟信号的相位以产生上升时钟信号和下降时钟信号;时钟延迟单元，被配置为响应于时钟信号延迟上升时钟信号和下降时钟信号 控制信号以产生延迟的上升时钟信号和延迟的下降时钟信号，占空比校正单元，被配置为产生校正上升时钟信号和校正下降时钟信号，该时钟信号响应于延迟的上升时钟信号的边沿定时而触发， 延迟下降时钟信号，以及延迟控制单元，被配置为检测校正上升时钟信号和校正下降时钟信号的占空比，以产生控制信号。

    RECEIVER CIRCUIT
    24.
    发明申请
    RECEIVER CIRCUIT 有权
    接收电路

    公开(公告)号：US20090149142A1

    公开(公告)日：2009-06-11

    申请号：US12179486

    申请日：2008-07-24

    申请人： Tae Jin Hwang ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang

    发明人： Tae Jin Hwang ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang

    IPC分类号： G06F3/033

    CPC分类号： G06F13/4072

    摘要： A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.

    摘要翻译： 接收机电路能够改善其操作特性。 接收器电路包括可变转换器，其被配置为在第一操作模式中在第一输出范围中输出偏移控制电压，并且根据测试模式激活信号在第二操作模式中将偏移控制电压输出到第二输出范围 以及感测放大器，被配置为基于灵敏度来感测输入数据，其中灵敏度由偏移控制电压控制。

    DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT
    28.
    发明申请
    DATA RECEIVER OF SEMICONDUCTOR INTEGRATED CIRCUIT 失效
    半导体集成电路的数据接收器

    公开(公告)号：US20090129459A1

    公开(公告)日：2009-05-21

    申请号：US12177829

    申请日：2008-07-22

    申请人： Hyung Soo Kim ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    发明人： Hyung Soo Kim ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee

    IPC分类号： H03K5/159

    CPC分类号： H03K19/09425

    摘要： A semiconductor integrated circuit equipped with an equalizer which has a circuit structure simpler than that of a related equalizer according to an FFE scheme or a DFE scheme and is capable of preventing a noise component from being amplified. The data receiver includes a plurality of receiver units, wherein each receiver unit includes a plurality of level detectors which detect different levels, and an encoder, in which the level detectors receive data according to a clock signal having a predetermined phase difference and perform an amplification operation including an equalization function based on feedback data, thereby outputting an amplification signal, and wherein level detectors of one receiver unit receive an amplification signal, as the feedback data, from level detectors of another receiver unit that receives a first clock signal having a phase more advanced than a phase of a second clock signal received in one receiver unit.

    摘要翻译： 一种配备有均衡器的半导体集成电路，其具有比根据FFE方案或DFE方案的相关均衡器的电路结构简单的电路结构，并且能够防止噪声分量被放大。 数据接收机包括多个接收机单元，其中每个接收机单元包括检测不同电平的多个电平检测器和编码器，其中电平检测器根据具有预定相位差的时钟信号接收数据并执行放大 操作包括基于反馈数据的均衡功能，从而输出放大信号，并且其中一个接收器单元的电平检测器从另一接收器单元的电平检测器接收作为反馈数据的放大信号，该接收器单元接收具有相位的第一时钟信号 比在一个接收机单元中接收的第二时钟信号的相位更先进。

    DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS
    29.
    发明申请
    DATA OUTPUT CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS 有权
    半导体存储器的数据输出电路

    公开(公告)号：US20090067278A1

    公开(公告)日：2009-03-12

    申请号：US12169568

    申请日：2008-07-08

    申请人： Hae Rang Choi ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Ji Wang Lee

    发明人： Hae Rang Choi ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Tae Jin Hwang ,  Ji Wang Lee

    IPC分类号： G11C8/08

    CPC分类号： G11C7/1051 ,  G11C7/1057 ,  G11C29/028 ,  G11C29/1201 ,  G11C29/50

    摘要： A data output circuit for a semiconductor memory apparatus includes a driver control signal generating unit that has a plurality of control signal generating units, each of which generates a driver unit control signal in response to a test signal during a test, and generates the driver unit control signal according to whether or not a fuse is cut after the test is completed, a first driver that has a plurality of driver units, each of which is activated in response to the driver unit control signal to drive a first data signal as an input signal and to output the driven first data signal to an output node, a signal combining unit that generates a first driver control signal in response to the driver unit control signal and an enable signal, and a second driver that has a plurality of driver units, each of which is activated in response to the first driver control signal to drive a second data signal as an input signal and to output the driven second data signal to the output node, and the number of driver units being two or more times as much as the number of driver units in the first driver. A voltage level on the output node is the voltage level of an output signal.

    摘要翻译： 一种用于半导体存储装置的数据输出电路，包括具有多个控制信号生成单元的驱动器控制信号生成单元，每个控制信号生成单元响应于测试期间的测试信号生成驱动单元控制信号，并且生成驱动单元 根据在测试完成之后是否切断熔丝的控制信号，具有多个驱动单元的第一驱动器，每个驱动器单元响应于驱动单元控制信号被激活以驱动第一数据信号作为输入 信号并将驱动的第一数据信号输出到输出节点;响应于驱动单元控制信号和使能信号产生第一驱动器控制信号的信号组合单元，以及具有多个驱动器单元的第二驱动器， 其中的每一个响应于第一驱动器控制信号被激活，以驱动第二数据信号作为输入信号，并将驱动的第二数据信号输出到输出节点;以及 驱动器单元的数量是第一驱动器中的驱动器单元的数量的两倍或更多倍。 输出节点上的电压电平是输出信号的电压电平。