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80 条记录 (耗时 0.056 秒)

    RECEIVER CIRCUIT
    1.
    发明申请
    RECEIVER CIRCUIT 有权
    接收电路

    公开(公告)号：US20090149142A1

    公开(公告)日：2009-06-11

    申请号：US12179486

    申请日：2008-07-24

    申请人： Tae Jin Hwang ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang

    发明人： Tae Jin Hwang ,  Kun Woo Park ,  Yong Ju Kim ,  Hee Woong Song ,  Ic Su Oh ,  Hyung Soo Kim ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang

    IPC分类号： G06F3/033

    CPC分类号： G06F13/4072

    摘要： A receiver circuit is capable of improving its operating characteristics. The receiver circuit includes a variable converter configured to output off-set control voltages in a first output range in a first operation mode and output the off-set control voltages in a second output range in a second operation mode according to a test mode activation signal, and a sense amplifier configured to sense input data based on a sensitivity, wherein the sensitivity is controlled by the off-set control voltages.

    摘要翻译： 接收机电路能够改善其操作特性。 接收器电路包括可变转换器，其被配置为在第一操作模式中在第一输出范围中输出偏移控制电压，并且根据测试模式激活信号在第二操作模式中将偏移控制电压输出到第二输出范围 以及感测放大器，被配置为基于灵敏度来感测输入数据，其中灵敏度由偏移控制电压控制。

    DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION
    6.
    发明申请
    DUTY CYCLE CORRECTION CIRCUIT WITH REDUCED CURRENT CONSUMPTION 失效
    具有降低电流消耗的占空比校正电路

    公开(公告)号：US20090206901A1

    公开(公告)日：2009-08-20

    申请号：US12333193

    申请日：2008-12-11

    申请人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Jae Min Jang ,  Hyung Soo Kim ,  Ji Wang Lee ,  Chang Kun Park ,  Ic Su Oh ,  Hae Rang Choi ,  Tae Jin Hwang

    发明人： Hee Woong Song ,  Yong Ju Kim ,  Sung Woo Han ,  Jae Min Jang ,  Hyung Soo Kim ,  Ji Wang Lee ,  Chang Kun Park ,  Ic Su Oh ,  Hae Rang Choi ,  Tae Jin Hwang

    IPC分类号： H03K5/04

    CPC分类号： H03K5/1565

    摘要： A duty cycle correction circuit includes a signal generating unit including a first signal generating unit coupled to a power supply voltage terminal and configured to output a complementary output signal of an output signal in response to a clock signal, and a second signal generating unit coupled to the power supply voltage terminal and configured to output the output signal in response to a complementary clock signal of the clock signal; a variable resistor unit coupled between the first and second signal generating units configured to vary an amount of current flowing into the signal generating unit according to a duty correction control signal, the duty correction control signal having a voltage level determined based on a voltage level of the output signal; and a current source coupled between the variable resistor unit and a ground voltage terminal configured to supply current to the signal generating unit.

    摘要翻译： 一种占空比校正电路包括：信号产生单元，包括耦合到电源电压端并被配置为响应于时钟信号输出输出信号的互补输出信号的第一信号产生单元，以及耦合到 所述电源电压端子被配置为响应于所述时钟信号的互补时钟信号而输出所述输出信号; 耦合在第一和第二信号发生单元之间的可变电阻器单元，被配置为根据占空比校正控制信号改变流入信号生成单元的电流量，该占空比校正控制信号具有基于电压电平 输出信号; 以及耦合在可变电阻器单元和被配置为向信号产生单元提供电流的接地电压端子之间的电流源。

    DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS
    7.
    发明申请
    DATA ALIGNMENT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS 有权
    半导体存储器的数据对准电路

    公开(公告)号：US20100309732A1

    公开(公告)日：2010-12-09

    申请号：US12647174

    申请日：2009-12-24

    申请人： Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

    发明人： Hyung Soo Kim ,  Yong Ju Kim ,  Sung Woo Han ,  Hee Woong Song ,  Ic Su Oh ,  Tae Jin Hwang ,  Hae Rang Choi ,  Ji Wang Lee ,  Jae Min Jang ,  Chang Kun Park

    IPC分类号： G11C7/10 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1006 ,  G11C7/1012 ,  G11C7/1078 ,  G11C7/1087

    摘要： A data alignment circuit of a semiconductor memory apparatus for receiving and aligning parallel data group includes a first control unit, a second control unit, a first alignment unit and a second alignment unit. The first alignment unit generates a first control signal group in response to an address group, a clock signal, and a latency signal. The second control unit generates a second control signal group in response to the address group, the clock signal, and the latency signal. The first alignment unit aligns the parallel data group as a first serial data group in response to the first control signal group. The second alignment unit aligns the parallel data group as a second serial data group in response to the second control signal group.

    摘要翻译： 用于接收和对准并行数据组的半导体存储装置的数据对准电路包括第一控制单元，第二控制单元，第一对准单元和第二对准单元。 第一对准单元响应于地址组，时钟信号和等待时间信号产生第一控制信号组。 第二控制单元响应于地址组，时钟信号和等待时间信号产生第二控制信号组。 第一对准单元响应于第一控制信号组将并行数据组对准为第一串行数据组。 第二对准单元响应于第二控制信号组将并行数据组对准为第二串行数据组。