公开(公告)号：US09508821B2

公开(公告)日：2016-11-29

申请号：US14998092

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L29/51 ,  H01L29/16 ,  H01L29/45 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L23/522 ,  H01L29/49 ,  H01L21/768 ,  H01L29/66 ,  H01L21/283 ,  H01L23/528 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L21/76897 ,  H01L21/28123 ,  H01L21/28229 ,  H01L21/28255 ,  H01L21/283 ,  H01L21/28562 ,  H01L21/31105 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/42364 ,  H01L29/456 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US09305771B2

公开(公告)日：2016-04-05

申请号：US14137536

申请日：2013-12-20

Applicant: Intel Corporation

Inventor： Shakuntala Sundararajan ,  Nadia M. Rahhal-Orabi

IPC: H01L21/302 ,  H01L21/02

CPC classification number: H01L21/02063

Abstract: An embodiment includes a method comprising: etching a material to expose a metal component in a metal layer, which is located on a substrate, while the substrate is in an etch chamber that is under vacuum; and performing an ash process on the metal component while the substrate is still in the etch chamber that is still under vacuum; wherein the material includes at least one of a dielectric and a mask and the metal component includes at least one of an interconnect, a via, and a contact. Other embodiments are described herein.

Abstract translation: 一个实施例包括一种方法，包括：当衬底处于真空下的蚀刻室中时，蚀刻材料以暴露位于衬底上的金属层中的金属组分; 以及在所述衬底仍然处于仍处于真空状态的所述蚀刻室内的同时对所述金属部件执行灰过程; 其中所述材料包括电介质和掩模中的至少一种，并且所述金属部件包括互连，通孔和触点中的至少一个。 本文描述了其它实施例。