公开(公告)号：US20210184045A1

公开(公告)日：2021-06-17

申请号：US16713600

申请日：2019-12-13

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Walid M. HAFEZ ,  Nidhi NIDHI ,  Ting CHANG ,  Hsu-Yu CHANG ,  Tanuj TRIVEDI ,  Jeong Dong KIM ,  Babak FALLAHAZAD

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L21/02 ,  H01L21/265 ,  H01L21/8238

Abstract: Embodiments disclosed herein include nanoribbon and nanowire semiconductor devices. In an embodiment, the semiconductor device comprises a nanowire disposed above a substrate. In an embodiment, the nanowire has a first dopant concentration, and the nanowire comprises a pair of tip regions on opposite ends of the nanowire. In an embodiment, the tip regions comprise a second dopant concentration that is greater than the first dopant concentration. In an embodiment, the semiconductor device further comprises a gate structure over the nanowire. In an embodiment, the gate structure is wrapped around the nanowire, and the gate structure defines a channel region of the device. In an embodiment, a pair of source/drain regions are on opposite sides of the gate structure, and both source/drain regions contact the nanowire.

公开(公告)号：US20190356032A1

公开(公告)日：2019-11-21

申请号：US16461554

申请日：2016-12-30

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Chia-Hong JAN ,  Walid HAFEZ ,  Neville DIAS ,  Hsu-Yu CHANG ,  Roman OLAC-VAW ,  Chen-Guan LEE

IPC: H01P3/12 ,  H01P5/12 ,  H01P11/00 ,  H01L21/768 ,  H01L23/66 ,  H01L21/8234 ,  H01P3/127

Abstract: Embodiments of the invention include an electromagnetic waveguide and methods of forming the electromagnetic waveguide. In an embodiment the electromagnetic waveguide includes a first spacer and a second spacer. In an embodiment, the first and second spacer each have a reentrant profile. The electromagnetic waveguide may also include a conductive body formed between in the first and second spacer, and a void formed within the conductive body. In an additional embodiment, the electromagnetic waveguide may include a first spacer and a second spacer. Additionally, the electromagnetic waveguide may include a first portion of a conductive body formed along sidewalls of the first and second spacer and a second portion of the conductive body formed between an upper portion of the first portion of the conductive body. In an embodiment, the first portion of the conductive body and the second portion of the conductive body define a void through the electromagnetic waveguide.

公开(公告)号：US20190245098A1

公开(公告)日：2019-08-08

申请号：US16344226

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02236 ,  H01L21/02241 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

公开(公告)号：US20170162503A1

公开(公告)日：2017-06-08

申请号：US15327338

申请日：2014-08-19

Applicant: INTEL CORPORATION

Inventor： Roman OLAC-VAW ,  Walid HAFEZ ,  Chia-Hong JAN ,  Hsu-Yu CHANG ,  Ting CHANG ,  Rahul RAMASWAMY ,  Pei-Chi LIU ,  Neville DIAS

IPC: H01L23/525 ,  H01L29/78 ,  H01L29/423 ,  H01L21/768

Abstract: A MOS antifuse with an accelerated dielectric breakdown induced by a void or seam formed in the electrode. In some embodiments, the programming voltage at which a MOS antifuse undergoes dielectric breakdown is reduced through intentional damage to at least part of the MOS antifuse dielectric. In some embodiments, damage may be introduced during an etchback of an electrode material which has a seam formed during backfilling of the electrode material into an opening having a threshold aspect ratio. In further embodiments, a MOS antifuse bit-cell includes a MOS transistor and a MOS antifuse. The MOS transistor has a gate electrode that maintains a predetermined voltage threshold swing, while the MOS antifuse has a gate electrode with a void accelerated dielectric breakdown.