公开(公告)号：US20200066907A1

公开(公告)日：2020-02-27

申请号：US16317708

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Hsu-Yu CHANG ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/786

Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.

公开(公告)号：US20190237564A1

公开(公告)日：2019-08-01

申请号：US16344003

申请日：2016-12-12

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/66795 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/66 ,  H01L29/66356 ,  H01L29/66818 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/7851

Abstract: A transistor including a source and a drain each formed in a substrate; a channel disposed in the substrate between the source and drain, wherein the channel includes opposing sidewalls with a distance between the opposing sidewalls defining a width dimension of the channel and wherein the opposing sidewalls extend a distance below a surface of the substrate; and a gate electrode on the channel. A method of forming a transistor including forming a source and a drain in an area of a substrate; forming a source contact on the source and a drain contact on the drain; after forming the source contact and the drain contact, forming a channel in the substrate in an area between the source and drain, the channel including a body having opposing sidewalls separated by a length dimension; and forming a gate contact on the channel.

公开(公告)号：US20190245098A1

公开(公告)日：2019-08-08

申请号：US16344226

申请日：2016-12-13

Applicant: Intel Corporation

Inventor： Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L21/02236 ,  H01L21/02241 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66818 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78684

Abstract: A transistor including a channel disposed between a source and a drain, a gate electrode disposed on the channel and surrounding the channel, wherein the source and the drain are formed in a body on a substrate and the channel is separated from the body. A method of forming an integrated circuit device including forming a trench in a dielectric layer on a substrate, the trench including dimensions for a transistor body including a width; forming a channel material in the trench; recessing the dielectric layer to expose a first portion of the channel material; increasing a width dimension of the exposed channel material; recessing the dielectric layer to expose a second portion of the channel material; removing the second portion of the channel material; and forming a gate stack on the first portion of the channel material, the gate stack including a gate dielectric and a gate electrode.

公开(公告)号：US20180323260A1

公开(公告)日：2018-11-08

申请号：US15773536

申请日：2015-12-23

Applicant: Intel Corporation

Inventor： Hsu-Yu CHANG ,  Neville L. DIAS ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7848

Abstract: Embodiments of the present invention are directed to dual threshold voltage (VT) channel devices and their methods of fabrication. In an example, a semiconductor device includes a gate stack disposed on a substrate, the substrate having a first lattice constant. A source region and a drain region are formed on opposite sides of the gate electrode. A channel region is disposed beneath the gate stack and between the source region and the drain region. The source region is disposed in a first recess having a first depth and the drain region disposed in a second recess having a second depth. The first recess is deeper than the second recess. A semiconductor material having a second lattice constant different than the first lattice constant is disposed in the first recess and the second recess.

公开(公告)号：US20190304840A1

公开(公告)日：2019-10-03

申请号：US16317265

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Chen-Guan LEE ,  Everett S. CASSIDY-COMFORT ,  Joodong PARK ,  Walid M. HAFEZ ,  Chia-Hong JAN ,  Rahul RAMASWAMY ,  Neville L. DIAS ,  Hsu-Yu CHANG

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/66

Abstract: An apparatus comprising at least one transistor in a first area of a substrate and at least one transistor in a second area, a work function material on a channel region of each of the at least one transistor, wherein an amount of work function material in the first area is different than an amount of work function material in the second area. A method comprising depositing a work function material and a masking material on at least one transistor body in a first area and at least one in a second area; removing less than an entire portion of the masking material so that the portion of the work function material that is exposed in the first area is different than that exposed in the second area; removing the exposed work function material; and forming a gate electrode on each of the at least one transistor bodies.

公开(公告)号：US20190206980A1

公开(公告)日：2019-07-04

申请号：US16328704

申请日：2016-10-21

Applicant: Intel Corporation

Inventor： Chia-Hong JAN ,  Walid M. HAFEZ ,  Neville L. DIAS ,  Rahul RAMASWAMY ,  Hsu-Yu CHANG ,  Roman W. OLAC-VAW ,  Chen-Guan LEE

IPC: H01L49/02 ,  H01L21/306 ,  H01L21/285 ,  C23C16/455

CPC classification number: H01L28/24 ,  C23C16/45525 ,  H01L21/28556 ,  H01L21/30608 ,  H01L27/0629

Abstract: Fin-based thin film resistors, and methods of fabricating fin-based thin film resistors, are described. In an example, an integrated circuit structure includes a fin protruding through a trench isolation region above a substrate. The fin includes a semiconductor material and has a top surface, a first end, a second end, and a pair of sidewalls between the first end and the second end. An isolation layer is conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A resistor layer is conformal with the isolation layer conformal with the top surface, the first end, the second end, and the pair of sidewalls of the fin. A first anode cathode electrode is electrically connected to the resistor layer. A second anode or cathode electrode is electrically connected to the resistor layer.