公开(公告)号：US20200265098A1

公开(公告)日：2020-08-20

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06K9/62 ,  G06F17/16

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US20190317857A1

公开(公告)日：2019-10-17

申请号：US16395769

申请日：2019-04-26

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson ,  Srikanth Srinivasan

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: Technologies for providing error correction for row direction and column direction in a cross point memory include a memory that includes media access circuitry coupled to a memory media having a cross point architecture. The media access circuitry is configured to read, from the memory media, a column of data. Additionally, the media access circuitry is configured to read, from the memory media, column error correction code (ECC) check data appended to the column of data and perform error correction on the column of data with the column ECC check data to produce error-corrected data.

公开(公告)号：US20190266219A1

公开(公告)日：2019-08-29

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F7/78 ,  G06F9/38 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US20190227739A1

公开(公告)日：2019-07-25

申请号：US16369996

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F3/06 ,  G06F12/02 ,  G06F11/10 ,  G06F9/30

Abstract: Technologies for performing a hyper-dimensional operation in a memory of the compute device include a memory and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to a receipt of the query, a key hyper-dimensional vector associated with the query, perform a hyper-dimensional operation to determine a reference hyper-dimensional vector associated with a value to the key. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array of a hyper-dimensional vector table in the memory, identify a closest matching row in the stochastic associative array relative to the reference hyper-dimensional vector, wherein the closest matching row indicates a closest matching value hyper-dimensional vector, and output a value associated with the closest matching value hyper-dimensional vector.

公开(公告)号：US20190220735A1

公开(公告)日：2019-07-18

申请号：US16361432

申请日：2019-03-22

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Jawad B. Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06N3/063 ,  G06N3/04 ,  G06F3/06

CPC classification number: G06N3/063 ,  G06F3/0604 ,  G06F3/0659 ,  G06F3/0673 ,  G06N3/0472

Abstract: Technologies for efficiently performing memory augmented neural network (MANN) update operations includes a device with circuitry configured to obtain a key usable to search a memory associated with a memory augmented neural network for one or more data sets. The circuitry is also configured to perform a stochastic associative search to identify a group of data sets within the memory that satisfy the key and write to the identified group of data sets concurrently to update the memory augmented neural network.

公开(公告)号：US20190220202A1

公开(公告)日：2019-07-18

申请号：US16367320

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C29/52

Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) using error correction codes include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The compute device identifies, based on a search performed on the columns in the matrix, one or more candidate data sets. Each candidate data set corresponds to one of the rows in the matrix. The compute device performs an error correction operation on the identified one or more candidate data sets to determine whether the identified one or more candidate data sets is an exact match with the subset of the bit data.

公开(公告)号：US20190042401A1

公开(公告)日：2019-02-07

申请号：US16144459

申请日：2018-09-27

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F12/02 ,  G06F15/78 ,  G06F3/06

Abstract: Technologies for directly performing read and write operations on matrix data in a data storage device are disclosed. The data storage device receives a request to perform a read or write operation on matrix data stored in one or more memory units of the data storage device. Each memory unit is associated with a column address for the matrix data. The data storage device determines whether the request specifies to read or write a column or a row in the matrix data. The data storage device performs, in response to a determination that the request specifies to read or write a column in the matrix data, the read or write operation on the matrix data on the column.

公开(公告)号：US11989553B2

公开(公告)日：2024-05-21

申请号：US16867948

申请日：2020-05-06

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F16/23 ,  G06F7/58 ,  G06F9/30 ,  G06F16/13 ,  G06F16/22 ,  G06F16/2455 ,  G06F16/9535 ,  G06F16/9538 ,  H01L27/06

CPC classification number: G06F9/3001 ,  G06F7/58 ,  G06F9/30036 ,  G06F16/137 ,  G06F16/2255 ,  H01L27/0688

Abstract: Technologies for performing random sparse lifting and Procrustean orthogonal sparse hashing using column read-enabled memory include a device that has a memory that is column addressable and circuitry connected to the memory. The circuitry is configured to add a set of input data vectors to the memory as a set of binary dimensionally expanded vectors, including multiplying each input data vector with a projection matrix. The circuitry is also configured to produce a search hash code from a search data vector, including multiplying the search data vector with the projection matrix. Further, the circuitry is configured to determine a Hamming distance between the search hash code and each of the binary dimensionally expanded vectors.

公开(公告)号：US20230305709A1

公开(公告)日：2023-09-28

申请号：US18040145

申请日：2020-09-15

Applicant: Intel Corporation

Inventor： Dipanjan Sengupta ,  Mariano Tepper ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0673 ,  G06F3/0659

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to facilitate improved use of stochastic associative memory. Example instructions cause at least one processor to: generate a hash code for data to be stored in a stochastic associative memory (SAM); compare the hash code with centroids of clusters of data stored in the SAM; select a first one of the clusters corresponding to a first one of the centroids that is closest to the hash code; determine whether a selected number of hash codes stored in the SAM exceeds a threshold; in response to the selected number exceeding the threshold: query a controller for sizes of the clusters; and determine, based on the query, that a second one of the clusters includes an unbalanced size; and select a third one of the clusters to associate with a second number of hash codes corresponding to the second one of the clusters.

公开(公告)号：US11593263B2

公开(公告)日：2023-02-28

申请号：US16367321

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Richard Coulson

IPC: G06F12/06 ,  G06F12/02

Abstract: Technologies for addressing individual bits in memory include a device having a memory that includes partitions that each have tiles, in which each tile stores an individual bit. The device also includes circuitry to receive a request to access (e.g., read or write) a sequence of bits in a partition. The request specifies a logical row or column address. A corresponding tile is determined from the logical row or column address and for each bit in the sequence. The corresponding tile is accessed to read or write the bit therein.