公开(公告)号：US12113881B2

公开(公告)日：2024-10-08

申请号：US17485069

申请日：2021-09-24

Applicant: Intel Corporation

Inventor： Weiqiang Ma ,  Atul Kwatra ,  Stephen T. Palermo

IPC: H04L69/18 ,  H04L69/08

CPC classification number: H04L69/18 ,  H04L69/08

Abstract: Various approaches for the packet processing, and the use of templates for generating modification commands for packet processing, are discussed herein. In an example, operations performed by network packet processing circuitry include: obtaining a stream of packets; obtaining a packet modification template that provides at least one command to insert content within the packets and change the packets according to an output format of a network protocol; receiving parameters to modify the packet modification template; and applying the packet modification template to modify the packets. In further examples, application of the packet modification template is performed using multiple processing components arranged in parallel groups of serial pipelines, each of the serial pipelines applying a portion of the packet modification template within at least a first stage and a second stage in each of the serial pipelines.

公开(公告)号：US12034873B2

公开(公告)日：2024-07-09

申请号：US17435500

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Bhushan Girishkumar Parikh ,  Hari K. Tadepalli ,  Stephen T. Palermo ,  Thomas Joseph O'Dwyer ,  Abhilasha Bhargav-Spantzel ,  Ned M. Smith

IPC: H04L29/06 ,  H04L9/30 ,  H04L9/32

CPC classification number: H04L9/3268 ,  H04L9/3066 ,  H04L9/3218

Abstract: An apparatus operating as a certificate authority (CA) is described. The apparatus can perform operations including receiving, from a plurality of requesting devices, a request to join a group. The request can include identification information for the group and attestation evidence for the plurality of requesting devices. Responsive to receiving the request, the apparatus can provide a group certificate for the group to the plurality of requesting devices.

公开(公告)号：US11943280B2

公开(公告)日：2024-03-26

申请号：US17883011

申请日：2022-08-08

Applicant: Intel Corporation

Inventor： Mrittika Ganguli ,  Stephen T. Palermo ,  Valerie J. Parker

IPC: G06F15/16 ,  H04L67/10 ,  H04L67/12

CPC classification number: H04L67/10 ,  H04L67/12

Abstract: Various systems and methods for implementing a multi-access edge computing (MEC) based system to realize 5G Network Edge and Core Service Dimensioning using Machine Learning and other Artificial Intelligence Techniques, for improved operations and usage of computing and networking resources, and are disclosed herein. In an example, processing circuitry of a compute node on a network is used to analyze execution of an application to obtain operational data. The compute node then may modularize functions of the application based on the operational data to construct modularized functions. A phase transition graph is constructed using a machine-learning based analysis, the phase transition graph representing state transitions from one modularized function to another modularized function, where the phase transition graph is used to dimension the application by distributing the modularized functions across the network.

公开(公告)号：US11650851B2

公开(公告)日：2023-05-16

申请号：US16678888

申请日：2019-11-08

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Nikhil Gupta ,  Vasudevan Srinivasan ,  Christopher MacNamara ,  Sarita Maini ,  Abhishek Khade ,  Edwin Verplanke ,  Lokpraveen Mosur

IPC: G06F9/50 ,  G06F9/455

CPC classification number: G06F9/505 ,  G06F9/45558 ,  G06F9/5044 ,  G06F2009/4557 ,  G06F2009/45595

Abstract: Methods, apparatus, systems and machine-readable storage media of an edge computing device using an edge server CPU with dynamic deterministic scaling is disclosed. A processing circuitry arrangement includes processing circuitry with processor cores operating at a center base frequency and memory. The memory includes instructions configuring the processing circuitry to configure a first set of the processor cores of the CPU to switch the operating at the center base frequency to operating at a first modified base frequency, and a second set of the processor cores to switch the operating at the center base frequency to operating at a second modified base frequency. A same processor core within the first set or the second set can be configured to switch operating between the first modified base frequency or the second modified base frequency.

公开(公告)号：US20180275893A1

公开(公告)日：2018-09-27

申请号：US15465247

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Hang T. Nguyen ,  Stephen T. Palermo ,  John J. Browne ,  Chris MacNamara ,  Pradeepsunder Ganesh

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0647 ,  G06F11/008 ,  G06F11/20 ,  G06F11/203 ,  G06F11/2041 ,  G06F11/2043 ,  G06F11/2046

Abstract: Discussed herein are component redundancy systems, devices, and methods. A method to transfer a workload from a first component to a second component of a same device may include monitoring a wear indicator associated with the first component, and in response to an indication that the first component is stressed based on the wear indicator, transferring a workload of the first component to the second component.

公开(公告)号：US09910692B2

公开(公告)日：2018-03-06

申请号：US15006320

申请日：2016-01-26

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Scott P. Dubal ,  Trevor Cooper ,  Anjali S. Jain ,  Iosif Gasparakis ,  Jr-Shian Tsai ,  Mike Bursell ,  Pradeepsunder Ganesh ,  Parthasarathy Sangam ,  Jesse C. Brandeburg

IPC: G06F9/455 ,  G06F9/50

CPC classification number: G06F9/45558 ,  G06F9/5011 ,  G06F2009/45583 ,  G06F2009/45595

Abstract: The present disclosure is directed to enhanced virtual function capabilities in a virtualized network environment. In general, devices may comprise physical and virtualized resources. The physical resources may comprise at least a network adaptor that may handle incoming data from a network and outgoing data to the network. The virtualized resources may comprise at least one virtual machine (VM) and a corresponding interface. The corresponding interface may be one of a physical interface, a virtual interface or a “super” virtual interface. The physical interface may provide a first set of capabilities allowing the VM to access (e.g., control) at least the network adaptor. The virtual interface may provide a second set of capabilities that is a subset of the first set. The super virtual interface may provide a third set of capabilities including the second set of capabilities and at least one additional capability from the first set of capabilities.

公开(公告)号：US20170286142A1

公开(公告)日：2017-10-05

申请号：US15085454

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Scott P. Dubal ,  Rashmin N. Patel

IPC: G06F9/455 ,  H04L29/06

CPC classification number: G06F9/45558 ,  G06F2009/4557 ,  G06F2009/45595 ,  H04L63/0428

Abstract: Technologies for dynamically allocating acceleration units of a network device include a network device configured to determine a present compute usage value associated with a workload of the virtual machine, determine whether to accelerate the virtual machine as a function of the present compute usage and a compute capability usage limit, and select, in response to a determination to accelerate the virtual machine, an acceleration unit from one or more acceleration units, as a function of a type of the workload. Additionally, the network device is configured to allocate the identified acceleration unit. Other embodiments are described and claimed.

公开(公告)号：US12120595B2

公开(公告)日：2024-10-15

申请号：US17598165

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Chetan Hiremath ,  Rajesh Gadiyar ,  Jason K. Smith ,  Valerie J. Parker ,  Udayan Mukherjee ,  Neelam Chandwani ,  Francesc Guim Bernat ,  Ned M. Smith

IPC: H04W48/02 ,  H04B7/185 ,  H04B7/195 ,  H04W16/28 ,  H04W84/06

CPC classification number: H04W48/02 ,  H04B7/18519 ,  H04B7/18521 ,  H04B7/195 ,  H04W16/28 ,  H04W84/06

Abstract: Various approaches for the deployment and use of communication exclusion zones, defined for use with a satellite non-terrestrial network (including within a low-earth orbit satellite constellation), are discussed. In an example, defining and implementing a non-terrestrial communication exclusion zone includes: calculating based on a future orbital position of a low-earth orbit satellite vehicle, an exclusion condition for communications from the satellite vehicle; identifying, based on the exclusion condition and the future orbital position, a timing for implementing the exclusion condition for the communications from the satellite vehicle; and generating exclusion zone data for use by the satellite vehicle, the exclusion zone data indicating the timing for implementing the exclusion condition for the communications from the satellite vehicle.

公开(公告)号：US11973519B2

公开(公告)日：2024-04-30

申请号：US16909640

申请日：2020-06-23

Applicant: Intel Corporation

Inventor： Bhushan G. Parikh ,  Stephen T. Palermo

IPC: H03M7/30 ,  G06F17/18

CPC classification number: H03M7/3097 ,  G06F17/18 ,  H03M7/3084

Abstract: Examples described herein relate to an apparatus comprising a central processing unit (CPU) and an encoding accelerator coupled to the CPU, the encoding accelerator comprising an entropy encoder to determine normalized probability of occurrence of a symbol in a set of characters using a normalized probability approximation circuitry, wherein the normalized probability approximation circuitry is to output the normalized probability of occurrence of a symbol in a set of characters for lossless compression. In some examples, the normalized probability approximation circuitry includes a shifter, adder, subtractor, or a comparator. In some examples, the normalized probability approximation circuitry is to determine normalized probability by performance of non-power of 2 division without computation by a Floating Point Unit (FPU). In some examples, the normalized probability approximation circuitry is to round the normalized probability to a decimal.

公开(公告)号：US11775298B2

公开(公告)日：2023-10-03

申请号：US16933369

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Neelam Chandwani ,  Rany T. Elsayed ,  Udayan Mukherjee ,  Lokpraveen Mosur ,  Adwait Purandare

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3887

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.