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21.发明授权Digital-to-time converter and methods for generating phase-modulated signals 有权数字时间转换器和用于产生相位调制信号的方法公开(公告)号：US09071304B2
公开(公告)日：2015-06-30
申请号：US13969132
申请日：2013-08-16
Applicant: Intel IP Corporation
Inventor： Rotem Banin , Ofir Degani , Markus Schimper , Ashoke Ravi
CPC classification number: H04B1/0475 , H03F1/02 , H03F3/24 , H03M1/66 , H03M1/86 , H04B2001/045
Abstract: Embodiments of a digital-to-time converter (DTC) and methods for generating phase-modulated signals are generally described herein. In some embodiments, a divide by 2N+/−1 operation on an oscillator signal generates first and second divider signals, the first divider signal is sampled to provide a rising-edge correlated signal, a divider unit output signal is sampled to provide a falling edge correlated signal, and either the second divider signal or a delayed version of the second divider signal is provided as the divider unit output signal. A selection between the rising-edge and the falling-edge correlated signals generates edge signals. A fine phase-modulated output signal is generated based on an edge interpolation between a first and second edge signals.
Abstract translation: 数字 - 时间转换器（DTC）的实施例以及用于产生相位调制信号的方法在这里通常被描述。 在一些实施例中，对振荡器信号进行2N +/- 1次除法产生第一和第二除法器信号，对第一分频器信号进行采样以提供上升沿相关信号，对分频器单元输出信号进行采样以提供下降沿 并且第二除法器信号或第二除法器信号的延迟版本被提供作为除法器单元输出信号。 上升沿和下降沿相关信号之间的选择产生边沿信号。 基于第一和第二边缘信号之间的边缘内插产生精细的相位调制输出信号。
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公开(公告)号：US10680619B2
公开(公告)日：2020-06-09
申请号：US16170716
申请日：2018-10-25
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
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公开(公告)号：US20190068200A1
公开(公告)日：2019-02-28
申请号：US16170716
申请日：2018-10-25
Applicant: Intel IP Corporation
Inventor： Elan Banin , Roy Amel , Ran Shimon , Ashoke Ravi , Nati Dinur
Abstract: A Digital Phase Locked Loop (DPLL), including a Time-to-Digital Converter (TDC) configured generate quantized phase values of a controlled oscillator signal; and a frequency estimation circuit configured to receive the quantized phase values, determine wraparound phase of the quantized phase values, and estimate a frequency based on the quantized phase values and the wraparound phase.
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