公开(公告)号：US10223266B2

公开(公告)日：2019-03-05

申请号：US15364411

申请日：2016-11-30

申请人： International Business Machines Corporation

发明人： Robert A. Cordes ,  Hung Q. Le ,  Brian W. Thompto

IPC分类号： G06F12/00 ,  G06F12/0815 ,  G06F12/0811 ,  G06F12/0804 ,  G06F12/0875

摘要： A load store unit (LSU) in a processor core detects that new data produced by the processor core is ready to be drained to an L2 cache. In response to the LSU detecting that an earlier version of the new data is not stored in L1 cache, a memory controller sends the new data as L1 cache missed data to a store queue (STQ), where the STQ makes data available for deallocation from the STQ to the L2 cache. In response to determining that there is no newer data waiting to be stored in the STQ, or no cache line invalidate to the line containing the store data in the STQ that misses the cache, the memory controller maintains the new data in the STQ with a zombie stat bit that indicates that the new data is a zombie store entry that can be utilized by the processor core.

公开(公告)号：US10073697B2

公开(公告)日：2018-09-11

申请号：US15047023

申请日：2016-02-18

申请人： International Business Machines Corporation

发明人： Sundeep Chadha ,  Robert A. Cordes ,  David A. Hrusecky ,  Hung Q. Le ,  Jentje Leenstra ,  Dung Q. Nguyen ,  Brian W. Thompto ,  Albert J. Van Norstrand, Jr.

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0862 ,  G06F13/16 ,  G06F13/42

CPC分类号： G06F9/30047 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/0862 ,  G06F12/0875 ,  G06F13/1668 ,  G06F13/4282 ,  G06F2212/283 ,  G06F2212/452 ,  G06F2212/602 ,  G06F2212/62 ,  G06F2213/0042

摘要： Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

公开(公告)号：US10067763B2

公开(公告)日：2018-09-04

申请号：US14966075

申请日：2015-12-11

申请人： International Business Machines Corporation

发明人： Sundeep Chadha ,  Robert A. Cordes ,  David A. Hrusecky ,  Hung Q. Le ,  Jentje Leenstra ,  Dung Q. Nguyen ,  Brian W. Thompto ,  Albert J. Van Norstrand, Jr.

IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F12/0813 ,  G06F12/0842 ,  G06F12/0875 ,  G06F12/0862 ,  G06F13/16 ,  G06F13/42

摘要： Handling unaligned load operations, including: receiving a request to load data stored within a range of addresses; determining that the range of addresses includes addresses associated with a plurality of caches, wherein each of the plurality of caches are associated with a distinct processor slice; issuing, to each distinct processor slice, a request to load data stored within a cache associated with the distinct processor slice, wherein the request to load data stored within the cache associated with the distinct processor slice includes a portion of the range of addresses; executing, by each distinct processor slice, the request to load data stored within the cache associated with the distinct processor slice; and receiving, over a plurality of data communications busses, execution results from each distinct processor slice, wherein each data communications busses is associated with one of the distinct processor slices.

公开(公告)号：US10037229B2

公开(公告)日：2018-07-31

申请号：US15152257

申请日：2016-05-11

申请人： International Business Machines Corporation

发明人： Sundeep Chadha ,  Robert A. Cordes ,  David A. Hrusecky ,  Hung Q. Le ,  Elizabeth A. McGlone

IPC分类号： G06F9/46 ,  G06F9/50

CPC分类号： G06F9/5027 ,  G06F9/30043 ,  G06F9/3836 ,  G06F9/3861 ,  G06F9/3891 ,  G06F12/0875 ,  G06F2212/452

摘要： Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.