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    EARLY SHARED RESOURCE RELEASE IN SYMMETRIC MULTIPROCESSING COMPUTER SYSTEMS
    26.
    发明申请
    EARLY SHARED RESOURCE RELEASE IN SYMMETRIC MULTIPROCESSING COMPUTER SYSTEMS 有权
    在对称多媒体计算机系统中早期共享资源释放

    公开(公告)号：US20160239418A1

    公开(公告)日：2016-08-18

    申请号：US14621460

    申请日：2015-02-13

    申请人： International Business Machines Corporation

    发明人： Garrett M. Drapala ,  Vesselina K. Papazova ,  Robert J. Sonnelitter, III

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0833 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/084 ,  G06F12/0893 ,  G06F2212/1021 ,  G06F2212/1024 ,  G06F2212/621

    摘要： In one embodiment, a computer-implemented method includes detecting a cache miss for a cache line. A resource is reserved on each of one or more remote computing nodes, responsive to the cache miss. A request for a state of the cache line on the one or more remote computing nodes is broadcast to the one or more remote computing nodes, responsive to the cache miss. A resource credit is received from a first remote computing node of the one or more remote computing nodes, responsive to the request. The resource credit indicates that the first remote computing node will not participate in completing the request. The resource on the first remote computing node is released, responsive to receiving the resource credit from the first remote computing node.

    摘要翻译： 在一个实施例中，计算机实现的方法包括检测高速缓存行的高速缓存未命中。 响应于高速缓存未命中，在一个或多个远程计算节点的每一个上保留资源。 响应于高速缓存未命中，向一个或多个远程计算节点广播对一个或多个远程计算节点上的高速缓存行的状态的请求。 响应于该请求，从一个或多个远程计算节点的第一远程计算节点接收资源信用。 资源信用表示第一个远程计算节点不参与完成请求。 响应于从第一远程计算节点接收资源信用，第一远程计算节点上的资源被释放。

    MAINTAINING ORDER WITH PARALLEL ACCESS DATA STREAMS
    27.
    发明申请
    MAINTAINING ORDER WITH PARALLEL ACCESS DATA STREAMS 有权
    维护订单与并行访问数据流

    公开(公告)号：US20160217077A1

    公开(公告)日：2016-07-28

    申请号：US14606432

    申请日：2015-01-27

    申请人： International Business Machines Corporation

    发明人： Ekaterina M. Ambroladze ,  Timothy C. Bronson ,  Garrett M. Drapala ,  Michael Fee ,  Matthias Klein ,  Pak-kin Mak ,  Robert J. Sonnelitter, III ,  Gary E. Strait

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0855 ,  G06F12/0833 ,  G06F2212/1021 ,  G06F2212/608 ,  G06F2212/621

    摘要： Maintaining store order with high throughput in a distributed shared memory system. A request is received for a first ordered data store and a coherency check is initiated. A signal is sent that pipelining of a second ordered data store can be initiated. If a delay condition is encountered during the coherency check for the first ordered data store, rejection of the first ordered data store is signaled. If a delay condition is not encountered during the coherency check for the first ordered data store, a signal is sent indicating a readiness to continue pipelining of the second ordered data store.

    摘要翻译： 在分布式共享存储器系统中维护具有高吞吐量的存储顺序。 接收到针对第一有序数据存储的请求，并且启动一致性检查。 发送信号，可以启动第二个有序数据存储的流水线。 如果在第一有序数据存储器的一致性检查期间遇到延迟条件，则发信号通知第一有序数据存储器的拒绝。 如果在第一有序数据存储器的一致性检查期间没有遇到延迟条件，则发送指示准备继续流水线化第二有序数据存储的信号。

    Memory controlled operations under dynamic relocation of storage
    28.
    发明授权
    Memory controlled operations under dynamic relocation of storage 有权
    存储控制操作在动态重定位存储

    公开(公告)号：US09348524B1

    公开(公告)日：2016-05-24

    申请号：US14547639

    申请日：2014-11-19

    申请人： International Business Machines Corporation

    发明人： Timothy C. Bronson ,  Garrett M. Drapala ,  Michael F. Fee ,  Pak-Kin Mak ,  Arthur J. O'Neill ,  Robert J. Sonnelitter, III

    IPC分类号： G06F3/06 ,  G06F12/08

    CPC分类号： G06F12/0802 ,  G06F12/0811 ,  G06F12/0837 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/283

    摘要： A computing device is provided and includes a plurality of nodes. Each node includes multiple chips and a node controller at which the multiple chips are assignable to logical partitions. Each of the multiple chips includes processors and a memory unit configured to handle local memory operations originating from the processors. The node controller includes a dynamic memory relocation (DMR) mechanism configured to move data having a DMR storage increment address relative to a local one of the memory units without interrupting a processing of the data by at least one of the logical partitions. During movement of the data by the DMR mechanism, the memory units are disabled from handling the local memory operations matching the DMR storage increment address and the node controller handles the local memory operations matching the DMR storage increment address.

    摘要翻译： 提供了一种计算设备并且包括多个节点。 每个节点包括多个芯片和一个节点控制器，多个芯片可以分配到逻辑分区。 多个芯片中的每一个包括处理器和被配置为处理源自处理器的本地存储器操作的存储器单元。 节点控制器包括动态存储器重定位（DMR）机制，其被配置为移动具有相对于存储器单元中的本地存储器单元的DMR存储增量地址的数据，而不会中断至少一个逻辑分区对数据的处理。 在通过DMR机制移动数据期间，禁止存储器单元处理与DMR存储增量地址匹配的本地存储器操作，并且节点控制器处理与DMR存储器增量地址匹配的本地存储器操作。

    Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy
    29.
    发明授权
    Performance optimization and dynamic resource reservation for guaranteed coherency updates in a multi-level cache hierarchy 有权
    性能优化和动态资源预留，用于在多级缓存层次结构中保证一致性更新

    公开(公告)号：US08996819B2

    公开(公告)日：2015-03-31

    申请号：US13670843

    申请日：2012-11-07

    申请人： International Business Machines Corporation

    发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill ,  Robert J. Sonnelitter, III

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F12/0811

    摘要： A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.

    摘要翻译： 高速缓存包括高速缓存流水线，被配置为从芯片内高速缓存和多个与所述请求接收器耦合的状态机接收芯片外相关性请求的请求接收器。 高速缓存还包括耦合在多个状态机和高速缓存管线之间的仲裁器，并且被配置为优先考虑片外一致性请求，以及被配置为将从高速缓存流水线发送的一致性请求的数量计数到较低 级缓存。 当计数器超过预定限制时，高速缓存流水线停止发送一致性请求。

    Managing in-line store throughput reduction
    30.
    发明授权
    Managing in-line store throughput reduction 有权
    管理在线商店吞吐量减少

    公开(公告)号：US08930628B2

    公开(公告)日：2015-01-06

    申请号：US13682136

    申请日：2012-11-20

    申请人： International Business Machines Corporation

    发明人： Deanna P. Berger ,  Michael F. Fee ,  Christine C. Jones ,  Diana L. Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F12/14 ,  G06F12/08 ,  G06F9/52

    CPC分类号： G06F12/0811 ,  G06F9/524 ,  G06F12/0855 ,  G06F12/0897

    摘要： Various embodiments of the present invention manage a hierarchical store-through memory cache structure. A store request queue is associated with a processing core in multiple processing cores. At least one blocking condition is determined to have occurred at the store request queue. Multiple non-store requests and a set of store requests associated with a remaining set of processing cores in the multiple processing cores are dynamically blocked from accessing a memory cache in response to the blocking condition having occurred.

    摘要翻译： 本发明的各种实施例管理分层存储存储器高速缓存结构。 存储请求队列与多个处理核心中的处理核心相关联。 确定至少一个阻塞条件已经在存储请求队列中发生。 响应于发生的阻塞状态，多个非存储请求和与多个处理核心中的剩余处理核心集相关联的一组存储请求被动态阻止访问存储器高速缓存。