公开(公告)号：US5808225A

公开(公告)日：1998-09-15

申请号：US777250

申请日：1996-12-31

申请人： Susan J. Corwin ,  David J. Kaplan ,  Thomas D. Fletcher

发明人： Susan J. Corwin ,  David J. Kaplan ,  Thomas D. Fletcher

IPC分类号： G10H3/12 ,  G10H7/00

CPC分类号： G10H3/125 ,  G10H7/00 ,  G10H2210/066 ,  G10H2210/471 ,  G10H2250/571

摘要： A method for compressing music into a digital format. An audio signal that corresponds to music is received and converted from an analog signal to a digital signal. The audio signal is analyzed, and a tone is identified. The musical note and instrument that correspond to the tone are determined, and data elements that represent the musical note and instrument are then stored.

摘要翻译： 一种将音乐压缩成数字格式的方法。 对应于音乐的音频信号被接收并从模拟信号转换成数字信号。 分析音频信号，并且识别音调。 确定对应于音调的音符和乐器，然后存储表示音符和乐器的数据元素。

公开(公告)号：US5132564A

公开(公告)日：1992-07-21

申请号：US558935

申请日：1990-07-27

申请人： Thomas D. Fletcher ,  Emil N. Hahn

发明人： Thomas D. Fletcher ,  Emil N. Hahn

IPC分类号： H03K17/04 ,  H03K17/567 ,  H03K19/00 ,  H03K19/003 ,  H03K19/013 ,  H04L25/02

CPC分类号： H03K19/0136 ,  H03K19/001 ,  H03K19/00353

摘要： The driver circuit comprises drive means (Q2) for drawing an output current from a bus line (13) in a first state of the circuit. An output diode (S1) in the path of the output current is reverse biased in a second state of the circuit to isolate the drive means from the bus line. A control current (I.sub.Q2B) for the drive transistor is drawn from the bus line (13), beyond the output diode (S1). By this means, power dissipation (heat) within the driver circuit due to the control current is eliminated. The driver circuit also comprises means (26, S3, P1) for biasing the output during connection of the circuit to a live bus line, so as to reduce noise for other circuits connected to the bus line.

公开(公告)号：US09141586B2

公开(公告)日：2015-09-22

申请号：US13725268

申请日：2012-12-21

申请人： Warren E. Ferguson ,  Brian J. Hickmann ,  Thomas D. Fletcher

发明人： Warren E. Ferguson ,  Brian J. Hickmann ,  Thomas D. Fletcher

IPC分类号： G06F7/499 ,  G06F17/10 ,  G06F7/00

CPC分类号： G06F17/10 ,  G06F7/00 ,  G06F7/4991 ,  G06F7/49942 ,  G06F7/49968 ,  G06F7/49973 ,  G06F9/30014 ,  G06F9/30094

摘要： A mechanism for performing single-path floating-point rounding in a floating point unit is disclosed. A system of the disclosure includes a memory and a processing device communicably coupled to the memory. In one embodiment, the processing device comprises a floating point unit (FPU) to generate a plurality of status flags for a rounded value of a finite nonzero number. The plurality of status flags are generated based on the finite nonzero number without calculating the rounded value of the finite nonzero number. The plurality of status flags comprises an overflow flag and an underflow flag. The FPU determines whether a rounded value should be calculated for the finite nonzero number based on the plurality of status flags and whether the overflow flag is asserted. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is asserted, the FPU calculates the rounded value of the finite nonzero number based on an overflow rounding. Upon determining that the rounded value should be calculated for the finite nonzero number based on the plurality of status flags and that the overflow flag is not asserted, the FPU calculates the rounded value of the finite nonzero number based on a blended reduced precision rounding.

摘要翻译： 公开了一种用于在浮点单元中执行单路径浮点舍入的机构。 本公开的系统包括可通信地耦合到存储器的存储器和处理装置。 在一个实施例中，处理装置包括浮点单元（FPU），用于为有限非零数的舍入值生成多个状态标志。 在不计算有限非零数的舍入值的情况下，基于有限非零数生成多个状态标志。 多个状态标志包括溢出标志和下溢标志。 基于多个状态标志，FPU确定是否应针对有限非零数计算舍入值，以及是否断言溢出标志。 在确定对于基于多个状态标志的有限非零数量计算舍入值并且断言溢出标志时，FPU基于溢出舍入来计算有限非零数的舍入值。 在确定基于多个状态标志对于有限非零数进行舍入值计算并且不断言溢出标志时，FPU基于混合减少的精度舍入来计算有限非零数的舍入值。

公开(公告)号：US20140222883A1

公开(公告)日：2014-08-07

申请号：US13991892

申请日：2011-12-21

申请人： Jose-Alejandro Pineiro ,  Simon Rubanovich ,  Benny Eitan ,  Amit Gradstein ,  Thomas D. Fletcher

发明人： Jose-Alejandro Pineiro ,  Simon Rubanovich ,  Benny Eitan ,  Amit Gradstein ,  Thomas D. Fletcher

IPC分类号： G06F7/57 ,  G06F7/544

CPC分类号： G06F7/57 ,  G06F1/02 ,  G06F1/03 ,  G06F1/0356 ,  G06F7/544 ,  G06F7/552 ,  G06F9/30014 ,  G06F9/3832 ,  G06F2101/08 ,  G06F2101/10 ,  G06F2101/12 ,  G06F2207/5521

摘要： A math circuit for computing an estimate of a transcendental function is described. A lookup table storage circuit has stored therein several groups of binary values, where each group of values represents a respective coefficient of a first polynomial that estimates the function to a high precision. A computing circuit uses a portion of a binary value, that is also taken from one of the groups of values, to evaluate a second polynomial that estimates the function to a low precision. Other embodiments are also described and claimed.

摘要翻译： 描述了一种用于计算超验函数估计的数学电路。 查找表存储电路中存储有几组二进制值，其中每组值表示将功能估计为高精度的第一多项式的相应系数。 计算电路使用二进制值的一部分，其也取自值组中的一组，以评估将功能估计为低精度的第二多项式。 还描述和要求保护其他实施例。

公开(公告)号：US08676871B2

公开(公告)日：2014-03-18

申请号：US12890533

申请日：2010-09-24

申请人： Alex Pineiro ,  Thomas D. Fletcher ,  Brian J. Hickmann

发明人： Alex Pineiro ,  Thomas D. Fletcher ,  Brian J. Hickmann

IPC分类号： G06F1/02

CPC分类号： G06F9/3001 ,  G06F1/035 ,  G06F9/3895 ,  G06F2101/08 ,  G06F2101/10 ,  G06F2101/12

摘要： A semiconductor chip is described having a functional unit that can execute a first instruction and execute a second instruction. The first instruction is an instruction that multiplies two operands. The second instruction is an instruction that approximates a function according to C0+C1X2+C2X22. The functional unit has a multiplier circuit. The multiplier circuit has: i) a first input to receive bits of a first operand of the first instruction and receive bits of a C1 term of the second instruction; ii) a second input to receive bits of a second operand of the first instruction and receive bits of a X2 term of the second instruction.

摘要翻译： 描述了具有可执行第一指令并执行第二指令的功能单元的半导体芯片。 第一条指令是将两个操作数相乘的指令。 第二条指令是根据C0 + C1X2 + C2X22近似函数的指令。 功能单元具有乘法电路。 所述乘法器电路具有：i）第一输入，用于接收所述第一指令的第一操作数的比特并接收所述第二指令的C1项的比特; ii）用于接收第一指令的第二操作数的比特并接收第二指令的X2项的比特的第二输入。

公开(公告)号：US06573772B1

公开(公告)日：2003-06-03

申请号：US09608485

申请日：2000-06-30

申请人： Xia Dai ,  Thomas D. Fletcher

发明人： Xia Dai ,  Thomas D. Fletcher

IPC分类号： G11C700

CPC分类号： H03K5/1534 ,  H03K3/356139

摘要： A method and apparatus for generating multiple locked self-timed pulsed clock signals is disclosed. Race margins are reduced over separate clock generating circuits by sharing the necessary delay circuit elements between the multiple clock generating circuits. An edge is gated with a delayed edge to form the first clock pulse. A subsequent second clock pulse is generated by gating a partially-delayed edge with the first clock pulse, which minimizes race margins and pulse evaporation.

摘要翻译： 公开了一种用于产生多个锁定自定时脉冲时钟信号的方法和装置。 通过在多个时钟发生电路之间共享必要的延迟电路元件，在单独的时钟发生电路上减少了占空比。 边沿通过延迟边缘选通以形成第一个时钟脉冲。 通过使用第一时钟脉冲选通部分延迟的边缘来产生随后的第二时钟脉冲，其使竞赛边缘和脉冲蒸发最小化。

公开(公告)号：US06567836B1

公开(公告)日：2003-05-20

申请号：US09469426

申请日：1999-12-23

申请人： Thomas D. Fletcher

发明人： Thomas D. Fletcher

IPC分类号： G06F750

CPC分类号： G06F7/506 ,  G06F2207/386

摘要： Circuits for binary adders to efficiently skip a carry bit over two or more bit positions with two or more carry-skip paths. In one implementation, such a binary adder includes a network of carry-processing cells for producing kill, generate, and propagate signals and carry-skip cells for bypassing certain bit positions with dual-wire differential signal paths to provide high-speed processing of adding operations.

摘要翻译： 用于二进制加法器的电路，以有效地跳过具有两个或多个进位跳越路径的两个或多个位位置的进位位。 在一个实施方案中，这种二进制加法器包括一个进位处理单元的网络，用于产生杀死，产生和传播信号以及用双线差分信号路径旁路特定位位置的进位跳跃单元，以提供加速的高速处理 操作。

公开(公告)号：US06529635B1

公开(公告)日：2003-03-04

申请号：US08990419

申请日：1997-12-15

申请人： Susan Julia Corwin ,  Thomas D. Fletcher

发明人： Susan Julia Corwin ,  Thomas D. Fletcher

IPC分类号： G06K936

CPC分类号： G06T9/001

摘要： A method and apparatus for compressing a digitized image. Boundaries of regions within a digitized image are identified. Shapes are selected from a bank of shapes based on the identified boundaries to represent the regions. Position and size information based on the position and size of the regions within the digitized image are associated with the selected shapes. Values are transmitted indicating the selected shapes and the associated position and size information as a representation of the digitized image.

摘要翻译： 一种用于压缩数字化图像的方法和装置。 识别数字化图像内的区域的边界。 根据识别的边界从形状库中选择形状以表示区域。 基于数字化图像内的区域的位置和大小的位置和大小信息与所选择的形状相关联。 发送指示所选形状和相关联的位置和大小信息作为数字化图像的表示的值。

公开(公告)号：US06385631B1

公开(公告)日：2002-05-07

申请号：US09176618

申请日：1998-10-21

申请人： Feng Chen ,  Thomas D. Fletcher

发明人： Feng Chen ,  Thomas D. Fletcher

IPC分类号： G06F700

CPC分类号： G06F7/74

摘要： A low voltage swing priority encoder comprising pass cells to provide differential voltages indicative of the leading one of a binary tuple. A tree structure with bypass paths allows for the minimization of the number of pass cells in a signal propagation path so as to reduce signal delay. The pass cells are responsive to control voltages indicative of various Boolean functions of the binary tuple, and a pulse voltage signal is applied to the pass cells. In response to the control voltages and the pulse voltage signal, the pass cells provide differential voltages so that voltage swing of the differential voltages are kept below the supply voltage to reduce dynamic power dissipation. Sense amplifiers sense the differential voltages to provide the final logic level indicative of the leading one of the binary tuple.

摘要翻译： 低电压摆动优先编码器包括通过单元以提供指示二进制元组中的前导元件的差分电压。 具有旁路路径的树结构允许最小化信号传播路径中的传递单元的数量，以便减少信号延迟。 传递单元响应于指示二进制元组的各种布尔函数的控制电压，并且脉冲电压信号被施加到通过单元。 响应于控制电压和脉冲电压信号，通电单元提供差分电压，使得差分电压的电压摆幅保持低于电源电压以减小动态功耗。 感测放大器感测差分电压以提供指示二进制元组中的主要一个的最终逻辑电平。

公开(公告)号：US06346828B1

公开(公告)日：2002-02-12

申请号：US09607291

申请日：2000-06-30

申请人： Eitan Rosen ,  Thomas D. Fletcher

发明人： Eitan Rosen ,  Thomas D. Fletcher

IPC分类号： H03K1900

CPC分类号： G06F13/4072

摘要： A pulsed clock tri-state controller uses pulsed clock logic to control a tri-state bus driver. A clock shaper generates a pulsed clock bar signal. The pulsed clock tri-state controller utilizes the pulsed clock bar signal to sample a data input signal and an enable input signal into latches to generate a data signal and an enable signal for a tri-state bus driver. Receivers on the tri-state bus, such as latches or registers, are clocked using a locally generated pulsed clock bar signal from a local clock shaper. The pulsed clock tri-state controller, tri-state bus drivers, and the pulsed receivers provide an efficient method for transferring data over a tri-state bus.

摘要翻译： 脉冲时钟三态控制器使用脉冲时钟逻辑来控制三态总线驱动器。 时钟整形器产生脉冲时钟条信号。 脉冲时钟三态控制器利用脉冲时钟条信号将数据输入信号和使能输入信号采样到锁存器中，以产生三态总线驱动器的数据信号和使能信号。 三态总线上的接收器（例如锁存器或寄存器）使用本地生成的脉冲时钟信号从本地时钟整形器进行计时。 脉冲时钟三态控制器，三态总线驱动器和脉冲接收器提供了一种通过三态总线传输数据的有效方法。