公开(公告)号：US06346828B1

公开(公告)日：2002-02-12

申请号：US09607291

申请日：2000-06-30

申请人： Eitan Rosen ,  Thomas D. Fletcher

发明人： Eitan Rosen ,  Thomas D. Fletcher

IPC分类号： H03K1900

CPC分类号： G06F13/4072

摘要： A pulsed clock tri-state controller uses pulsed clock logic to control a tri-state bus driver. A clock shaper generates a pulsed clock bar signal. The pulsed clock tri-state controller utilizes the pulsed clock bar signal to sample a data input signal and an enable input signal into latches to generate a data signal and an enable signal for a tri-state bus driver. Receivers on the tri-state bus, such as latches or registers, are clocked using a locally generated pulsed clock bar signal from a local clock shaper. The pulsed clock tri-state controller, tri-state bus drivers, and the pulsed receivers provide an efficient method for transferring data over a tri-state bus.

摘要翻译： 脉冲时钟三态控制器使用脉冲时钟逻辑来控制三态总线驱动器。 时钟整形器产生脉冲时钟条信号。 脉冲时钟三态控制器利用脉冲时钟条信号将数据输入信号和使能输入信号采样到锁存器中，以产生三态总线驱动器的数据信号和使能信号。 三态总线上的接收器（例如锁存器或寄存器）使用本地生成的脉冲时钟信号从本地时钟整形器进行计时。 脉冲时钟三态控制器，三态总线驱动器和脉冲接收器提供了一种通过三态总线传输数据的有效方法。

公开(公告)号：US06667645B1

公开(公告)日：2003-12-23

申请号：US09467214

申请日：1999-12-20

申请人： Thomas D. Fletcher ,  Eitan Rosen

发明人： Thomas D. Fletcher ,  Eitan Rosen

IPC分类号： H03K3356

CPC分类号： H03K5/15013 ,  G06F1/10 ,  H03K19/0963

摘要： A signal transfer clocking circuit is disclosed which features a first stage including a first latch and a first, non-clocking circuit in series therewith and a second stage including a second, dynamic latch and at least a second circuit in series therewith. The first latch has a data input side and is opened in response to a first level of a pulse clock signal applied thereto to effect transfer of incoming data through the first stage in a first phase of operation of the signal transfer clocking circuit. The dynamic latch has a data input coupled to an output of the first circuit and is opened in response to a second level of the same or different pulse clock signal applied thereto as that applied to the first latch to effect transfer of data generated by the first stage, through the second stage, to at least one succeeding circuit, in a second, successive phase of operation of the signal transfer clocking circuit, the succeeding circuit being opened and closed by a clock signal having phase and frequency characteristics linked to that applied to the dynamic latch. The dynamic latch clocking methodology used in the signal transfer clocking circuit is particularly applicable to any traditional static latch circuits, such as CMOS static latch circuitry, although not limited thereto, to minimize min-delay race violations and to effect a skew-tolerant operation.

摘要翻译： 公开了一种信号传输时钟电路，其特征在于包括第一锁存器和与其串联的第一非时钟电路的第一级和包括第二动态锁存器和至少第二电路串联的第二级。 第一锁存器具有数据输入端，并且响应于施加到其上的脉冲时钟信号的第一电平而被打开以在信号传送时钟电路的第一操作阶段中实现通过第一级的输入数据的传送。 动态锁存器具有耦合到第一电路的输出的数据输入，并且响应于施加到第一电路的相同或不同的脉冲时钟信号的第二电平而被打开，以施加到第一电路施加的第二电平，以实现由第一电路产生的数据的传输 在第二阶段中，至少一个后续电路，在信号传送时钟电路的第二个连续的操作阶段中，后续电路被一个时钟信号打开和​​关闭，该时钟信号的相位和频率特性与 动态锁存器。 在信号传输时钟电路中使用的动态锁存时钟方法特别适用于任何传统的静态锁存电路，例如CMOS静态锁存电路，尽管不限于此，以最小化最小延迟竞争违规并实现偏斜容限操作。

公开(公告)号：US06192092B1

公开(公告)日：2001-02-20

申请号：US09094666

申请日：1998-06-15

申请人： Rommel O. Dizon ,  Thomas D. Fletcher ,  Javed S. Barkatullah ,  Eitan Rosen

发明人： Rommel O. Dizon ,  Thomas D. Fletcher ,  Javed S. Barkatullah ,  Eitan Rosen

IPC分类号： H04L700

CPC分类号： G06F1/10 ,  H03K5/133 ,  H04L7/0004 ,  H04L7/0008 ,  H04L7/0037

摘要： A method and apparatus to compensate for skew in a processor clock signal. A first clock signal at a first location in the processor is compared with a reference clock signal. The first clock signal is corrected based on the results of this comparison with the reference clock signal. The clock signal may be corrected by using a programmable delay compensator. A second clock signal at a second location in the processor may be compared with the corrected first clock signal and the second clock signal may be corrected based on the results of the comparison. The compensators may be permanently programmed as required using fuses associated with compensator control bits.

摘要翻译： 一种补偿处理器时钟信号中的偏斜的方法和装置。 将处理器中的第一位置处的第一时钟信号与参考时钟信号进行比较。 基于与参考时钟信号进行比较的结果来校正第一时钟信号。 可以通过使用可编程延迟补偿器来校正时钟信号。 处理器中的第二位置处的第二时钟信号可以与校正的第一时钟信号进行比较，并且可以基于比较的结果校正第二时钟信号。 补偿器可以根据需要使用与补偿器控制位相关联的保险丝进行永久编程。

公开(公告)号：US08727049B1

公开(公告)日：2014-05-20

申请号：US13528703

申请日：2012-06-20

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： B60W10/06 ,  B60W10/08 ,  B60W10/24

CPC分类号： B60W10/06 ,  B60W10/08 ,  B60W10/26 ,  B60W20/12 ,  B60W50/0097 ,  B60W2050/0089 ,  B60W2510/244 ,  B60W2520/10 ,  B60W2550/402 ,  B60W2710/244 ,  Y02T10/6291

摘要： Embodiments of the present disclosure provide a method comprising providing a first adaptive threshold of charge for a battery within a hybrid vehicle and based upon the first adaptive threshold of charge for the battery, operating the hybrid vehicle in a mode of operation. The method also comprises automatically analyzing at least one condition and based upon the automatically analyzing at least one condition, automatically altering the first adaptive threshold of charge for the battery to provide a second adaptive threshold of charge for the battery that is different from the first adaptive threshold. Based upon automatically altering the first adaptive threshold of charge for the battery to provide a second adaptive threshold of charge for the battery, (i) a proportional use of power to be supplied by a fuel engine component and/or (ii) a proportional use of power to be supplied by an electric engine component is automatically altered.

摘要翻译： 本公开的实施例提供了一种方法，包括为混合动力车辆内的电池提供充电的第一自适应阈值，并且基于电池的第一充电自适应阈值，以操作模式操作混合动力车辆。 该方法还包括自动分析至少一个条件并且基于自动分析至少一个条件，自动改变电池的第一充电自适应阈值，以提供不同于第一适应性的电池的第二充电自适应阈值 阈。 基于自动改变电池的电荷的第一自适应阈值以为电池提供第二适应性充电阈值，（i）比例地使用由燃料发动机部件提供的功率和/或（ii）比例使用 由电动发动机部件供给的动力被自动改变。

公开(公告)号：US08145856B1

公开(公告)日：2012-03-27

申请号：US13149349

申请日：2011-05-31

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G06F12/00

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/30141

摘要： A processor circuit including a register file system that has a number of register file elements. Each of the register file elements has an input/output port, a register file cell, and a special memory element. The register file cell and the special memory element are clocked by an advance thread signal. Data stored in the register file cell propagates to the special memory element according to the advance thread signal. In this manner, state information for multiple threads may be stored.

摘要翻译： 一种包括具有多个寄存器文件元素的寄存器文件系统的处理器电路。 每个寄存器文件元素具有输入/输出端口，寄存器文件单元和特殊存储器元件。 寄存器文件单元和特殊存储元件由提前线程信号计时。 存储在寄存器文件单元中的数据根据​​提前线程信号传播到特殊存储器元件。 以这种方式，可以存储多个线程的状态信息。

公开(公告)号：US08076946B1

公开(公告)日：2011-12-13

申请号：US12124812

申请日：2008-05-21

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G01R35/00

CPC分类号： G01R19/00 ,  G01R31/3008 ,  G01R35/00 ,  H03K19/0013

摘要： An integrated circuit and a method for efficiently operating integrated circuit devices. The integrated circuit includes an input that is configured to receive a first current which is representative of a leakage current drawn by leakage in a portion of the integrated circuit. The integrated circuit includes a leakage calibrator that is configured to compare the first current to a current required to perform a switching operation and output a value indicative of the leakage.

摘要翻译： 集成电路和用于有效地操作集成电路器件的方法。 集成电路包括被配置为接收表示在集成电路的一部分中由泄漏引起的泄漏电流的第一电流的输入。 集成电路包括泄漏校准器，其被配置为将第一电流与执行开关操作所需的电流进行比较并输出指示泄漏的值。

公开(公告)号：US07958323B1

公开(公告)日：2011-06-07

申请号：US12118390

申请日：2008-05-09

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G06F12/00

CPC分类号： G06F9/3851 ,  G06F9/30123 ,  G06F9/30141

摘要： A processor having a multithreading memory system, including a main memory element, at least one special memory element and a controller. The main memory element may be configured to receive a data signal and a control signal. The at least one special memory element may be associated with the main memory element. Further, the special memory element may be configured to receive an output signal from the main memory element. The controller may be configured to receive an output signal from the at least one special memory element and a scan input signal. Further, the controller may be further configured to select one of the output signal from the at least one special memory element and the scan input signal based on an advance thread signal. The selected one of the output signal from the at least one special memory element and the scan input signal may be forwarded to the main memory element as the control signal.

摘要翻译： 一种具有多线程存储器系统的处理器，包括主存储元件，至少一个特殊存储器元件和控制器。 主存储器元件可以被配置为接收数据信号和控制信号。 该至少一个特殊存储元件可以与主存储元件相关联。 此外，特殊存储元件可以被配置为从主存储元件接收输出信号。 控制器可以被配置为从至少一个特殊存储元件和扫描输入信号接收输出信号。 此外，控制器还可以被配置为基于提前线程信号来选择来自至少一个特殊存储元件的输出信号和扫描输入信号中的一个。 来自至少一个特殊存储元件的输出信号和扫描输入信号中所选择的一个可以作为控制信号被转发到主存储元件。

公开(公告)号：US07525341B1

公开(公告)日：2009-04-28

申请号：US11093080

申请日：2005-03-28

申请人： Eitan Rosen ,  Dan Lieberman

发明人： Eitan Rosen ,  Dan Lieberman

IPC分类号： H03K19/173 ,  H03K3/37 ,  G06F7/38

CPC分类号： H03K19/00323 ,  H03K17/005

摘要： Methods and apparatus are provided for time-balanced switching of multiplexer circuits. An embodiment of the invention includes a transistor chain coupled to the output of the multiplexer circuit. The transistor chain preferably delays transitions that would otherwise occur relatively quickly, to match the timing of transitions that occur relatively slowly. The timing of relatively slow transitions is left unaltered. The invention advantageously allows all selector input transitions to yield a data output transition with a substantially constant delay.

摘要翻译： 提供了多路复用器电路的时间平衡切换的方法和装置。 本发明的实施例包括耦合到多路复用器电路的输出的晶体管链。 晶体管链优选地延迟否则将相对快速地发生的转变，以匹配相对缓慢地发生的转变的定时。 相对较慢的转换的时间保持不变。 本发明有利地允许所有选择器输入转换以基本恒定的延迟产生数据输出转换。

公开(公告)号：US06822479B1

公开(公告)日：2004-11-23

申请号：US10292872

申请日：2002-11-13

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： H03K19094

CPC分类号： H03K19/003

摘要： An intregrated circuit includes at least one I/O buffer. This buffer includes a first supply logic portion, connectable to a core voltage supply and an I/O voltage supply, and a second I/O buffer portion adapted to receive an activation signal from the first supply logic portion. The first supply logic portion is modified to act to prevent the output of an activation signal until the core voltage is supplied to the integrated circuit.

摘要翻译： 集成电路包括至少一个I / O缓冲器。 该缓冲器包括可连接到核心电压源和I / O电压源的第一电源逻辑部分，以及适于从第一电源逻辑部分接收激活信号的第二I / O缓冲器部分。 第一电源逻辑部分被修改为用于防止激活信号的输出，直到核心电压被提供给集成电路。

公开(公告)号：US08058900B1

公开(公告)日：2011-11-15

申请号：US12423281

申请日：2009-04-14

申请人： Eitan Rosen

发明人： Eitan Rosen

IPC分类号： G06F7/38

CPC分类号： H03K19/096 ,  G06F1/06

摘要： Aspects of the disclosure provide a clock gate circuit for generating a clock signal. The clock gate circuit can include a multiplexer configured to receive a first logic signal at a first data input, a second logic signal at a second data input, and a reference clock signal at a selector input, and to output the clock signal having a logic state selected from one of the first logic signal or the second logic signal based on transitions of the reference clock signal. Further, the clock gate circuit can include a logic module coupled to the multiplexer and configured to output the first logic signal and the second logic signal based on an enable signal and the output of the multiplexer.

摘要翻译： 本公开的方面提供了一种用于产生时钟信号的时钟门电路。 时钟门电路可以包括多路复用器，其被配置为在第一数据输入处接收第一逻辑信号，在第二数据输入处接收第二逻辑信号，并在选择器输入处接收参考时钟信号，并输出具有逻辑 状态根据参考时钟信号的转变从第一逻辑信号或第二逻辑信号之一中选择。 此外，时钟门电路可以包括耦合到多路复用器的逻辑模块，并且被配置为基于使能信号和多路复用器的输出来输出第一逻辑信号和第二逻辑信号。