公开(公告)号：US07609548B2

公开(公告)日：2009-10-27

申请号：US11858907

申请日：2007-09-21

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/10

摘要： The present invention relates to a method of programming a multi level cell capable of storing above 1 data bit. The method includes storing first data in a first storing unit, storing second data in a second storing unit, programming a least significant bit data in accordance with the data stored in the first and second storing units, and programming a most significant bit data in accordance with the data stored in the first and second storing units following the program of the least significant bit data.

摘要翻译： 本发明涉及一种编程能够存储1位以上数据位的多级单元的方法。 该方法包括：将第一数据存储在第一存储单元中，将第二数据存储在第二存储单元中，根据存储在第一和第二存储单元中的数据编程最低有效位数据，以及根据 其中存储在第一和第二存储单元中的数据遵循最低有效位数据的程序。

公开(公告)号：US07466598B2

公开(公告)日：2008-12-16

申请号：US11617673

申请日：2006-12-28

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/3418

摘要： A method of programming a NAND flash memory device includes providing a flash memory device, wherein word lines are disposed between a drain selecting line and a source selecting line, wherein a first word line is provided adjacent to the source selecting line and a last word line is provided adjacent to the drain selecting line; and selecting a word line to program memory cells coupled to the selected word line to perform an even LSB program operation and an odd LSB program operation for the selected first word line. Each of the word lines is selected until all of the word lines have been selected, so that the even LSB program operation and the odd LSB program operation can be performed for all of the word lines. The even LSB program operation is performed to store a lower rank data bit in memory cells coupled to an even bit line assigned a selected word line. The odd LSB program operation is performed to store a lower rank data bit in memory cells coupled to an odd bit line assigned to the selected word line.

摘要翻译： 一种对NAND闪速存储器件进行编程的方法包括提供闪存器件，其中字线设置在漏极选择线和源极选择线之间，其中第一字线被设置成与源极选择线相邻，而最后一个字线 设置在漏极选择线附近; 以及选择字线以对耦合到所选字线的存储器单元进行编程，以对所选择的第一字线执行偶数LSB编程操作和奇数LSB编程操作。 选择每个字线直到所有字线都被选择为止，从而可以对所有字线执行偶数LSB编程操作和奇数LSB编程操作。 执行偶数LSB编程操作以将低等级数据位存储在耦合到分配了选定字线的偶位线的存储器单元中。 执行奇数LSB编程操作以将低等级数据位存储在耦合到分配给所选字线的奇位位线的存储单元中。

公开(公告)号：US07379342B2

公开(公告)日：2008-05-27

申请号：US11304433

申请日：2005-12-14

申请人： Seong Je Park ,  Seung Ho Chang

发明人： Seong Je Park ,  Seung Ho Chang

IPC分类号： G11C11/34

CPC分类号： G11C16/12 ,  G11C16/3454 ,  G11C16/3459

摘要： A program operation and a program verification operation are repeatedly performed. The program verification operation is performed on memory cells including pass cells to obtain a uniform distribution characteristic of a threshold voltage. Furthermore, the program verification operation is performed with a compare voltage being set higher than a target voltage initially so that a threshold voltage of a memory cell is sufficiently higher than the target voltage. The program verification operation is again performed lowering the compare voltage according to the repetition number. Thus, normally programmed cells are prevented from being again excessively programmed.

摘要翻译： 重复执行程序操作和程序验证操作。 在包括通过单元的存储单元上执行程序验证操作，以获得阈值电压的均匀分布特性。 此外，程序验证操作以比初始设定为高于目标电压的比较电压进行，使得存储单元的阈值电压足够高于目标电压。 程序验证操作再次根据重复次数降低比较电压。 因此，防止正常编程的单元被过度编程。

公开(公告)号：US20080101116A1

公开(公告)日：2008-05-01

申请号：US11926130

申请日：2007-10-29

申请人： Jin Yong Seong ,  Seong Je Park

发明人： Jin Yong Seong ,  Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C16/12 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： A multi-level cell copyback program method in a non-volatile memory device is disclosed. The method includes reading LSB data of a source page, and storing the read LSB data in a second register of a page buffer, transmitting the data stored in the second register to a first register coupled to a data inputting circuit, and storing the transmitted data in the first register, amending the data stored in the first register through the data inputting circuit, transmitting the amended data to the second register, and storing the transmitted data in the second register, and LSB-programming corresponding data to a target page in accordance with the data stored in the second register.

摘要翻译： 公开了一种在非易失性存储器件中的多级单元复制程序方法。 该方法包括读取源页的LSB数据，并将读出的LSB数据存储在页缓冲器的第二寄存器中，将存储在第二寄存器中的数据发送到耦合到数据输入电路的第一寄存器，并存储发送数据 在第一寄存器中，通过数据输入电路对存储在第一寄存器中的数据进行修改，将修正的数据发送到第二寄存器，并将发送的数据存储在第二寄存器中，并且将对应数据LSB编程到目标页面 数据存储在第二个寄存器中。

公开(公告)号：US20080080237A1

公开(公告)日：2008-04-03

申请号：US11858907

申请日：2007-09-21

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C16/10

摘要： The present invention relates to a method of programming a multi level cell capable of storing above 1 data bit. The method includes storing first data in a first storing unit, storing second data in a second storing unit, programming a least significant bit data in accordance with the data stored in the first and second storing units, and programming a most significant bit data in accordance with the data stored in the first and second storing units following the program of the least significant bit data.

摘要翻译： 本发明涉及一种编程能够存储1位以上数据位的多级单元的方法。 该方法包括：将第一数据存储在第一存储单元中，将第二数据存储在第二存储单元中，根据存储在第一和第二存储单元中的数据编程最低有效位数据，以及根据 其中存储在第一和第二存储单元中的数据遵循最低有效位数据的程序。

公开(公告)号：US20070165465A1

公开(公告)日：2007-07-19

申请号：US11306072

申请日：2005-12-15

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C29/00 ,  G11C7/00 ,  G11C17/18

CPC分类号： G11C29/812

摘要： A repair I/O fuse circuit of a semiconductor memory device includes a reduced by as much as half layout area of fuses by replacing what one repair I/O information is represented by existing two I/O fuses with what one repair I/O information is represented by one I/O fuse. The repair I/O fuse circuit includes a plurality of I/O fuse circuits, each having one fuse. A repair signal indicates that there is an address to be replaced. If a chip enable signal is activated, each of the plurality of I/O fuse circuits outputs a repair I/O information signal depending on whether a fuse has been cut.

摘要翻译： 半导体存储器件的修复I / O保险丝电路包括通过用现有的两个I / O保险丝代替一个修复I / O信息来代替什么是修复I / O信息的一个修复I / O信息，减少多达一半的保险丝布局面积 由一个I / O保险丝表示。 修理I / O熔丝电路包括多个I / O熔丝电路，每个具有一个熔丝。 修复信号表示存在要更换的地址。 如果芯片使能信号被激活，则多个I / O熔丝电路中的每一个根据熔丝是否被切断而输出修复I / O信息信号。

公开(公告)号：US08508992B2

公开(公告)日：2013-08-13

申请号：US13177603

申请日：2011-07-07

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/0483

摘要： A method of operating a semiconductor memory device includes performing an LSB program operation for selected memory cells while raising a program voltage, when the threshold voltages of some of the selected memory cells reach a target level, storing data, corresponding to a relevant program voltage, in a first flag cell, performing the LSB program operation for some of the selected memory cells, having threshold voltages not reached the target level, until the threshold voltages of all the selected memory cells reach the target level, and after the LSB program operation is completed, performing an MSB program operation for the selected memory cells by using a program voltage, set based on the data stored in the first flag cell, as a start program voltage.

摘要翻译： 一种操作半导体存储器件的方法包括当所选择的一些存储器单元的阈值电压达到目标电平时，对应于相关编程电压存储数据，在提高编程电压的同时，对所选存储单元执行LSB编程操作， 在第一标志单元中，对具有阈值电压未达到目标电平的一些所选择的存储单元执行LSB编程操作，直到所有所选存储单元的阈值电压达到目标电平，并且在LSB编程操作为 通过使用基于存储在第一标志单元中的数据设置的编程电压作为开始编程电压，对所选存储单元执行MSB编程操作。

公开(公告)号：US08498161B2

公开(公告)日：2013-07-30

申请号：US13183675

申请日：2011-07-15

申请人： Jung Hwan Lee ,  Seong Je Park

发明人： Jung Hwan Lee ,  Seong Je Park

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C7/1048 ,  G11C7/12 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C2211/5634 ,  G11C2211/5642

摘要： A read method of a nonvolatile memory device according to an exemplary embodiment of this disclosure includes precharging bit lines coupled to memory cells, performing a first read operation by supplying a first reference voltage to the memory cells in order to determine the data stored in the memory cells, precharging bit lines coupled to undetermined memory cells whose data has not been determined by the first read operation, and performing a second read operation by supplying a second reference voltage to the memory cells in order to determine data stored in the undetermined memory cells.

摘要翻译： 根据本公开的示例性实施例的非易失性存储器件的读取方法包括预先充电与存储器单元耦合的位线，通过向存储器单元提供第一参考电压来执行第一读取操作，以便确定存储在存储器中的数据 单元，预充电位线，其耦合到其数据尚未被第一读取操作确定的未确定存储单元，以及通过向存储器单元提供第二参考电压来执行第二读取操作，以便确定存储在未确定的存储器单元中的数据。

公开(公告)号：US20130033933A1

公开(公告)日：2013-02-07

申请号：US13204119

申请日：2011-08-05

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C16/10 ,  G11C16/06 ,  G11C16/04

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

摘要： Techniques and devices relating to adjusting one or more operational parameters for memory cells are provided. One such device may include a detection unit configured to perform one or more reading operations on a set of memory cells to determine an upper bound of the threshold voltages of the set of memory cells. The device may further include a parameter adjustment unit configured to adjust one or more operational parameters for the set of memory cells based, at least in part, on the determined upper bound of the threshold voltages. Other techniques and devices are also provided.

摘要翻译： 提供了与调整存储器单元的一个或多个操作参数相关的技术和设备。 一个这样的设备可以包括被配置为对一组存储器单元执行一个或多个读取操作以确定该组存储器单元的阈值电压的上限的检测单元。 该装置还可以包括参数调整单元，其被配置为至少部分地基于所确定的阈值电压的上限来调整该组存储器单元的一个或多个操作参数。 还提供了其他技术和设备。

公开(公告)号：US08369155B2

公开(公告)日：2013-02-05

申请号：US12953235

申请日：2010-11-23

申请人： Seong Je Park

发明人： Seong Je Park

IPC分类号： G11C16/04

CPC分类号： G11C16/3459 ,  G11C16/0483 ,  G11C16/3404 ,  G11C16/3445

摘要： A method of verifying a non-volatile memory device to increase the read margin even though a negative verifying voltage is not applied is disclosed. The method of verifying a non-volatile memory device includes coupling a cell string to a bit line precharged to a high level through a sensing node, the cell string being provided between a common source line and the bit line; applying a verifying voltage to a plurality of word lines associated with the cell string; disconnecting the bit line from the sensing node; coupling the common source line to the cell string while the verifying voltage is applied to the word lines, wherein the common source line is applied with a bias voltage higher than a ground voltage; and coupling the bit line to the sensing node so as to detect a level of the bit line.

摘要翻译： 公开了即使未施加负的验证电压来验证非易失性存储器件来增加读取余量的方法。 验证非易失性存储器件的方法包括通过感测节点将单元串耦合到预充电到高电平的位线，该单元串被提供在公共源极线和位线之间; 将验证电压施加到与所述单元串相关联的多个字线; 断开位线与感测节点的连接; 将所述公共源极线耦合到所述单元串，同时将所述验证电压施加到所述字线，其中所述公共源极线施加高于接地电压的偏置电压; 并将位线耦合到感测节点，以便检测位线的电平。