公开(公告)号：US20050041346A1

公开(公告)日：2005-02-24

申请号：US10644718

申请日：2003-08-20

Applicant: Yi-Hsun Wu ,  Jian-Hsing Lee

Inventor： Yi-Hsun Wu ,  Jian-Hsing Lee

IPC: H01L23/60 ,  H01L27/02 ,  H02H9/00

CPC classification number: H01L27/0285

Abstract: A sensor for electrostatic discharge (ESD) protection includes a voltage divider and a device coupled thereto. The sensor is coupled to an input terminal of the sensor, wherein a voltage drop occurs across the voltage divider and a high state voltage is generated at an output terminal of the sensor when an ESD voltage pulse is applied to the input terminal of the sensor. The device maintains the high state voltage at the output terminal of the sensor, while the ESD voltage pulse is applied to the input terminal of the sensor. A method for ESD protection includes the step of pulling down a gate terminal of a MOS transistor of an ESD circuit to a low state voltage when an ESD pulse is sensed.

Abstract translation: 用于静电放电（ESD）保护的传感器包括分压器和与其耦合的装置。 传感器耦合到传感器的输入端，其中在分压器上发生电压降，并且当ESD电压脉冲施加到传感器的输入端时，在传感器的输出端产生高的状态电压。 该装置在传感器的输出端保持高状态电压，同时将ESD电压脉冲施加到传感器的输入端。 ESD保护的方法包括当感测到ESD脉冲时将ESD电路的MOS晶体管的栅极端子下拉到低状态电压的步骤。

公开(公告)号：US06747857B1

公开(公告)日：2004-06-08

申请号：US10062706

申请日：2002-02-01

Applicant: Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

Inventor： Jian-Hsing Lee ,  Hung-Der Su ,  Jiaw-Ren Shih

IPC: H02H900

CPC classification number: H03K17/0822 ,  H01L27/0266 ,  H03K17/6872

Abstract: A novel device and process is described for an ESD protection device for complimentary cascaded NMOS output circuit strings. The invention consists of a clamping NMOS with gate connected to the input or output pad through a diode and connected to ground through a resistor. The clamping device drain is connected to the signal gate of the active output NMOS and the clamping device source is connected to ground. An ESD event causes the diode to go into breakdown mode and the conduction current across the resistor places a positive voltage on the clamping device gate turning the clamping device on. This clamps the active NMOS signal gate to ground assuring that the output NMOS remains in an off condition during the ESD event. This prevents any damage due to high current flow through the active, or used output inverter string.

Abstract translation: 对于用于互补级联的NMOS输出电路串的ESD保护器件描述了一种新颖的器件和工艺。 本发明包括一个钳位NMOS，其栅极通过二极管连接到输入或输出焊盘，并通过电阻器连接到地。 钳位装置漏极连接到有源输出NMOS的信号栅极，钳位装置源连接到地。 ESD事件导致二极管进入击穿模式，并且电阻两端的导通电流在夹紧装置门上施加正电压，使夹紧装置打开。 这将有源NMOS信号栅极钳位到地，确保在ESD事件期间输出NMOS保持关断状态。 这可以防止由于高电流流过有源或使用的输出逆变器串造成的任何损坏。

公开(公告)号：US06730968B1

公开(公告)日：2004-05-04

申请号：US10205520

申请日：2002-07-25

Applicant: Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Yi-Hsu Wu ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L2362

CPC classification number: H01L27/0292 ,  H01L27/0251 ,  H01L2924/0002 ,  H01L2924/00

Abstract: This invention provides two circuit embodiments for a whole chip electrostatic discharge, ESD, protection scheme. It also includes a method for whole chip ESD protection. This invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths. The advantage of this invention is the ability to create a parallel discharge path to ground in order to discharge the damaging ESD current quickly so as to avoid circuit damage. The two circuit embodiments show how the protection circuits of this invention at both the unzapped I/O pads and the zapped I/O pad are connected in a parallel circuit for discharging ESD currents quickly. These protection embodiments require a small amount of semiconductor area, since the smaller protection circuits are distributed and placed at the locations of each I/O pad.

Abstract translation: 本发明提供了用于整个芯片静电放电，ESD保护方案的两个电路实施例。 它还包括一种全芯片ESD保护方法。 本发明涉及将本发明的电路分配给每个输入/输出焊盘，以便提供并联的ESD电流放电路径。 本发明的优点是能够快速地形成对地的平行放电路径，以便有效地放电损坏的ESD电流，以避免电路损坏。 两个电路实施例示出了本发明的保护电路如何在未分离的I / O焊盘和已加热的I / O焊盘两端均以并联电路连接，以快速放电ESD电流。 这些保护实施例需要少量的半导体区域，因为较小的保护电路分布并放置在每个I / O焊盘的位置。

公开(公告)号：US06653709B2

公开(公告)日：2003-11-25

申请号：US10213612

申请日：2002-08-07

Applicant: Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

Inventor： Yi-Hsu Wu ,  Hung-Der Su ,  Jian-Hsing Lee ,  Boon-Khim Liew

IPC: H01L2972

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L27/0266

Abstract: A new cascaded NMOS transistor output circuit with enhanced ESD protection is achieved. A driver PMOS transistor has the source connected to a voltage supply, the gate connected to the input signal, and the drain connected to the output pad. A dummy PMOS transistor has the source and the gate connected to the voltage supply, and the drain connected to the output pad. A driver NMOS cascaded stack comprises first and second NMOS transistors. The first NMOS transistor has the source connected to ground and the gate connected to the input signal. The second NMOS transistor has the gate connected to the voltage supply, the source connected to the first NMOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source. A dummy NMOS cascaded stack comprises third and fourth NMOS transistors. The third NMOS transistor has the gate and the source connected to ground. The fourth NMOS transistor has the gate connected to the voltage supply, the source connected to the third MOS transistor drain, and the drain connected to the output pad. A p− implanted region underlies the n+ region of the drain but does not underlie the n+ region of the source.

公开(公告)号：US06614078B2

公开(公告)日：2003-09-02

申请号：US10147272

申请日：2002-05-16

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-Hung Chen ,  Ping-Lung Liao

IPC: H01L2976

CPC classification number: H01L21/823878 ,  H01L27/0921

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

公开(公告)号：US06479872B1

公开(公告)日：2002-11-12

申请号：US09221959

申请日：1998-12-28

Applicant: Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

Inventor： Tao Cheng ,  Jian-Hsing Lee ,  Lin-June Wu

IPC: H01L2362

CPC classification number: H01L27/0266

Abstract: A dynamic source coupled ESD protection circuit that dissipates an ESD voltage coupled to an electrical contact pad to protect internal circuits on an integrated circuits chip is described. The ESD protection circuit lowers the snapback voltage of the ESD protection circuit to allow a thinner gate oxide within the internal circuits of the integrated circuit chip. The dynamic substrate coupled electrostatic discharge protection circuit consists of a gated MOS transistor, a capacitor, and a resistor. The gated MOS transistor has a drain region connected to the electrical contact pad. The gate and source are connected to a power supply voltage source. The power supply voltage source will either be a substrate biasing voltage or ground reference point for a gated NMOS transistor. The power supply voltage source will be the power supply voltage source VDD for the gated PMOS transistor. The capacitor has a first plate connected to the electrical contact pad, and a second plate connected to said substrate bulk region of the MOS transistor. The resistor is a polycrystalline silicon resistor that is connected between the second plate of the capacitor and the power supply voltage source.

Abstract translation: 描述了动态源耦合ESD保护电路，其消耗耦合到电接触焊盘的ESD电压以保护集成电路芯片上的内部电路。 ESD保护电路降低ESD保护电路的回跳电压，以便在集成电路芯片的内部电路内允许更薄的栅极氧化物。 动态衬底耦合静电放电保护电路由门控MOS晶体管，电容器和电阻组成。 门控MOS晶体管具有连接到电接触焊盘的漏极区域。 栅极和源极连接到电源电压源。 电源电压源将是门控NMOS晶体管的衬底偏置电压或接地参考点。 电源电压源将是门控PMOS晶体管的电源电压源VDD。 电容器具有连接到电接触焊盘的第一板和连接到MOS晶体管的所述衬底主体区域的第二板。 电阻器是连接在电容器的第二板和电源电压源之间的多晶硅电阻器。

公开(公告)号：US06420221B1

公开(公告)日：2002-07-16

申请号：US09507646

申请日：2000-02-22

Applicant: Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

Inventor： Jian-Hsing Lee ,  Jiaw-Ren Shih ,  Shui-hung Chen ,  Ping-Lung Liao

IPC: H01L218238

CPC classification number: H01L21/823878 ,  H01L27/0921

Abstract: CMOS I/O structures are described which are latchup-immune by inserting p+ and n+ diffusion guard-rings into the NMOS and PMOS source side of a semiconductor substrate, respectively. P+ diffusion guard-rings surround individual n-channel transistors and n+ diffusion guard-rings surround individual p-channel transistors. These guard-rings, connected to voltage supplies, reduce the shunt resistances of the parasitic SCRs, commonly associated with CMOS structures, from either the p-substrate to p+ guard-ring or the n-well to n+ guard-ring. In a second preferred embodiment a deep p+ implant is implanted into the p+ guard-ring or p-well pickup to decrease the shunt resistances of the parasitic SCRs. The n+ and p+ guard-rings, like the guard-rings of the first preferred embodiment, are connected to positive and negative voltage supplies, respectively. In either of the two preferred embodiments the reduced shunt resistances prevent the forward biasing of the parasitic bipolar transistors of the SCR, thus insuring that the holding voltage is larger than the supply voltage.

Abstract translation: 通过将p +和n +扩散保护环分别插入到半导体衬底的NMOS和PMOS源极侧中，分别描述了通过插入 - 免疫的CMOS I / O结构。 P +扩散保护环围绕各个n沟道晶体管，n +扩散保护环围绕着单独的p沟道晶体管。 连接到电源的这些保护环通过p型衬底到p +保护环或n阱到n +保护环，降低了与CMOS结构通常相关的寄生SCR的分流电阻。 在第二优选实施例中，将深p +注入植入到p +保护环或p阱拾取器中以降低寄生SCR的分流电阻。 与第一优选实施例的保护环相同的n +和p +保护环分别连接到正和负电压源。 在两个优选实施例中的任一个中，减小的分流电阻防止SCR的寄生双极晶体管的正向偏置，从而确保保持电压大于电源电压。

公开(公告)号：US5903499A

公开(公告)日：1999-05-11

申请号：US928227

申请日：1997-09-12

Applicant: Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chou Ho

Inventor： Kuo-Reay Peng ,  Jian-Hsing Lee ,  Juang-Ke Yeh ,  Ming-Chou Ho

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by first applying a moderately high positive voltage pulse to the source of the EEPROM cell. Simultaneously, a first relatively large negative voltage is applied to the control gate. While a ground reference potential is applied to the semiconductor substrate. At this same time the drain is floating. The flash EEPROM cell is then detrapped by floating the source and drain and applying the ground reference potential to the semiconductor substrate. At the same time a second relatively large negative voltage pulse is applied to the control gate.

Abstract translation: 一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除快闪EEPROM单元的方法是首先向EEPROM单元的源极施加适度高的正电压脉冲。 同时，向控制栅极施加第一相对较大的负电压。 同时对半导体衬底施加接地参考电位。 在同一时间，排水沟漂浮。 然后通过漂浮源极和漏极并将接地参考电位施加到半导体衬底来去除快闪EEPROM单元。 同时，向控制栅极施加第二相对大的负电压脉冲。

公开(公告)号：US5838618A

公开(公告)日：1998-11-17

申请号：US927472

申请日：1997-09-11

Applicant: Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

Inventor： Jian-Hsing Lee ,  Juang-Ker Yeh ,  Kuo-Reay Peng ,  Ming-Chou Ho

IPC: G11C16/14 ,  G11C16/04 ,  G11C7/00

CPC classification number: G11C16/14

Abstract: A method to erase data from a flash EEPROM while electrical charges trapped in the tunneling oxide of a flash EEPROM are eliminated to maintain proper separation of the programmed threshold voltage and the erased threshold voltage after extended programming and erasing cycles. The method to erase a flash EEPROM cell begins by channel erasing to remove charge from the floating gate of the flash EEPROM cell. The channel erasing consists of applying a first relatively large negative voltage pulse to the control gate of said EEPROM cell and concurrently applying a first moderately large positive voltage pulse to a first diffusion well. At the same time a ground reference potential is applied to the semiconductor substrate, while the drain and a second diffusion well is allowed to float. The method to erase then proceeds with the source erasing to detrap the tunneling oxide of the flash EEPROM cell. The source erasing consists continued floating the drain and the second diffusion well and concurrently applying the ground reference potential to the semiconductor substrate and the first diffusion well. Concurrently a second relatively large negative voltage pulse is applied to the control gate, as a second moderately large positive voltage pulse is applied to said source.

Abstract translation: 一种在闪存EEPROM的隧道氧化物中捕获电荷的情况下从闪存EEPROM擦除数据的方法被消除，以便在扩展编程和擦除周期之后保持编程阈值电压和擦除阈值电压的适当分离。 擦除闪存EEPROM单元的方法是从通道擦除开始，以从闪存EEPROM单元的浮动栅极去除电荷。 通道擦除包括将第一相对较大的负电压脉冲施加到所述EEPROM单元的控制栅并且同时向第一扩散阱施加第一适度大的正电压脉冲。 同时，对半导体衬底施加接地参考电位，同时使漏极和第二扩散阱浮动。 擦除的方法然后继续进行源擦除以去除快速EEPROM单元的隧穿氧化物。 源擦除继续浮置漏极和第二扩散阱，同时将接地参考电位施加到半导体衬底和第一扩散阱。 同时，向控制栅极施加第二相对较大的负电压脉冲，因为向所述源施加第二适度大的正电压脉冲。

公开(公告)号：US5565790A

公开(公告)日：1996-10-15

申请号：US387084

申请日：1995-02-13

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L27/02 ,  H02H9/04 ,  H01L23/62

CPC classification number: H01L27/0266 ,  H01L27/0251

Abstract: An improved ESD protection circuit of the type having a field transistor connected as a clamp between ground and a pad to be protected and an FET trigger circuit that is connected between ground and a node where the protected circuits are connected. A resistor interconnects the pad and the node. The trigger FET turns on when a high ESD voltage causes avalanche breakdown and charge carriers from the trigger FET turn on the field transistor clamp. Before the field transistor clamp turns on, oxide breakdown in the gate oxide of the FET occurs. A resistor is connected between the gate electrode and ground to limit the current through the oxide during the time for the avalanche to develop and for the clamp to turn on.

Abstract translation: 一种改进的ESD保护电路，其具有连接在接地和待保护的焊盘之间的钳位的场晶体管，以及连接在地和被保护电路连接的节点之间的FET触发电路。 电阻器使焊盘和节点互连。 当高ESD电压引起雪崩击穿时，触发FET导通，并且来自触发FET的电荷载流子导通场晶体管钳位。 在场晶体管钳位导通之前，FET的栅极氧化物发生氧化物击穿。 电阻器连接在栅电极和地之间以限制在雪崩发展的时间期间通过氧化物的电流，并且钳位器导通。