公开(公告)号：US06604184B2

公开(公告)日：2003-08-05

申请号：US09344267

申请日：1999-06-30

申请人： Achmed R. Zahir ,  Gary N. Hammond ,  John H. Crawford

发明人： Achmed R. Zahir ,  Gary N. Hammond ,  John H. Crawford

IPC分类号： G06F1200

CPC分类号： G06F12/1009

摘要： The present invention is a method and apparatus to map virtual memory space. A region register file provides a region identifier for a virtual address in the virtual memory space. The virtual address includes a virtual region number and a virtual page number. A virtual page table look-up circuit is coupled to the region register file to generate a page table entry (PTE) virtual address from virtual address parameters. The virtual address parameters include the virtual address.

摘要翻译： 本发明是一种映射虚拟存储器空间的方法和装置。 区域寄存器文件为虚拟存储器空间中的虚拟地址提供区域标识符。 虚拟地址包括虚拟区号和虚拟页号。 虚拟页表查找电路耦合到区域寄存器文件以从虚拟地址参数生成页表项（PTE）虚拟地址。 虚拟地址参数包括虚拟地址。

公开(公告)号：US09857858B2

公开(公告)日：2018-01-02

申请号：US13976817

申请日：2012-05-17

申请人： Devadatta V. Bodas ,  John H. Crawford ,  Alan G. Gara

发明人： Devadatta V. Bodas ,  John H. Crawford ,  Alan G. Gara

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3209 ,  G06F1/3234

摘要： A method and system for managing power consumption and performance of computing systems are described herein. The method includes monitoring an overall power consumption of the computing systems to determine whether the overall power consumption is above or below an overall power consumption limit, and monitoring a performance of each computing system to determine whether the performance is within a performance tolerance. The method further includes adjusting the power consumption limits for the computing systems or the performances of the computing systems such that the overall power consumption is below the overall power consumption limit and the performance of each computing system is within the performance tolerance.

公开(公告)号：US09778720B2

公开(公告)日：2017-10-03

申请号：US13976545

申请日：2011-12-30

申请人： Anil K. Kumar ,  John H. Crawford ,  Paul S. Diefenbaugh

发明人： Anil K. Kumar ,  John H. Crawford ,  Paul S. Diefenbaugh

IPC分类号： G06F1/00 ,  G06F1/32 ,  G06F3/00 ,  G06F13/12 ,  G06F11/30

CPC分类号： G06F1/3206 ,  G06F1/3203 ,  G06F1/3215 ,  G06F1/3234 ,  G06F1/325 ,  G06F11/3051

摘要： An apparatus, system, and method, the method including receiving an indication of a idle state capability of a platform connected device; determining, by a chipset, an idle power state compatible with the device; and directing the device to enter the determined idle power state based on a power state of the chipset.

公开(公告)号：US07984248B2

公开(公告)日：2011-07-19

申请号：US11027623

申请日：2004-12-29

申请人： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

发明人： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

IPC分类号： G06F12/00

CPC分类号： G06F9/528 ,  G06F9/3834 ,  G06F9/544

摘要： The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

摘要翻译： 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。

公开(公告)号：US20110161627A1

公开(公告)日：2011-06-30

申请号：US12647671

申请日：2009-12-28

申请人： Justin J. Song ,  John H. Crawford

发明人： Justin J. Song ,  John H. Crawford

IPC分类号： G06F15/76 ,  G06F9/30 ,  G06F9/06 ,  G06F12/00

CPC分类号： G06F1/3203 ,  G06F9/5094 ,  Y02D10/22

摘要： An apparatus and method is described herein for avoiding inefficient core hopping and providing hardware assisted power state selection. Future idle-activity of cores is predicted. If the residency of activity patterns for efficient core hop scenarios is predicted to be large enough, a core is determined to be efficient and allowed. However, if efficient activity patterns are not predicted to be resident for long enough—inefficient patterns are instead predicted to be resident for longer—then a core hop request is denied. As a result, designers may implement a policy for avoiding core hops that weighs the potential gain of the core hop, such as alleviation of a core hop condition, against a penalty for performing the core hop, such as a temporal penalty for the core hop. Separately, idle durations associated with hardware power states for cores may be predicted in hardware. Furthermore, accuracy of the idle duration prediction is determined. Upon receipt of a request for a core to enter a power state, a power management unit may select either the hardware predicted power state, if the accuracy is high enough, or utilize the requested power state, if the accuracy of the hardware prediction is not high enough.

摘要翻译： 这里描述了一种用于避免低效的核心跳跃并提供硬件辅助电源状态选择的装置和方法。 预测未来的核心空闲活动。 如果预期高效核心跳情景的活动模式的居住地位足够大，则确定核心是有效的并被允许的。 然而，如果高效的活动模式不被预测为居民，因为足够长时间而不是预期为较长时间驻留，则核心跳跃请求被拒绝。 因此，设计人员可以实施一种策略，以避免核心跳跃的权重，核心跳跃的权重可能会降低核心跳跃条件的潜在收益，而不考虑执行核心跳的惩罚，例如核心跳的时间损失 。 另外，与硬件的硬件电源状态相关联的空闲持续时间可以在硬件中预测。 此外，确定空闲持续时间预测的精度。 在接收到核心进入电源状态的请求时，如果硬件预测的准确度不是，功率管理单元可以选择硬件预测功率状态，如果精度足够高，或者利用所请求的功率状态 足够高。

公开(公告)号：US07669009B2

公开(公告)日：2010-02-23

申请号：US10950279

申请日：2004-09-23

申请人： Sailesh Kottapalli ,  John H. Crawford

发明人： Sailesh Kottapalli ,  John H. Crawford

IPC分类号： G06F12/08

CPC分类号： G06F12/128 ,  G06F12/0811 ,  G06F12/123

摘要： A method and apparatus for selecting and updating a replacement candidate in a cache is disclosed. In one embodiment, a cache miss may initiate the eviction of a present replacement candidate in a last-level cache. The cache miss may also initiate the selection of a future replacement candidate. Upon the selection of the future replacement candidate, the corresponding cache line may be invalidated in lower-level caches but remain resident in the last-level cache. The future replacement candidate may be updated by subsequent hits to the replacement candidate in the last-level cache prior to a subsequent cache miss.

摘要翻译： 公开了一种用于选择和更新高速缓存中的替换候选的方法和装置。 在一个实施例中，高速缓存未命中可以在最后一级高速缓存中启动对当前替换候选者的驱逐。 高速缓存未命中还可以启动未来替换候选者的选择。 在选择将来的替换候选者之后，相应的高速缓存行可能在较低级别的高速缓存中被无效，但仍然驻留在最后一级高速缓存中。 在随后的高速缓存未命中之前，可以通过对最后一级高速缓存中的替换候选者的后续命中来更新未来替换候选。

公开(公告)号：US06654909B1

公开(公告)日：2003-11-25

申请号：US09608959

申请日：2000-06-30

申请人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

发明人： Nhon T. Quach ,  John H. Crawford ,  Chakravarthy Kosaraju ,  Venkatesh Nagapudi

IPC分类号： G06F1100

CPC分类号： G06F11/073 ,  G06F11/0751 ,  G06F11/1064 ,  G06F12/1036

摘要： The invention relates to the design of highly reliable microprocessors and more specifically to the use of a dedicated state machine that periodically checks the validity of critical processor resources. In an embodiment of the present invention, an apparatus to detect errors in information stored in a processor resource includes an error detection component, which is configured to control the detection of errors in the information stored in the processor resource; and a comparison component coupled to the error detection component, which is configured to receive the information from the processor resource and inputs from the detection component. The comparison component is further configured to determine if the information is valid, and to output a signal to replace the information if the information if invalid.

摘要翻译： 本发明涉及高度可靠的微处理器的设计，更具体地涉及使用周期性地检查关键处理器资源的有效性的专用状态机。 在本发明的实施例中，检测存储在处理器资源中的信息中的错误的装置包括：错误检测部件，被配置为控制对存储在处理器资源中的信息中的错误的检测; 以及耦合到所述错误检测组件的比较组件，其被配置为从所述处理器资源接收所述信息并从所述检测组件输入。 所述比较部件还被配置为确定所述信息是否有效，并且如果所述信息是无效的，则输出信号以替换所述信息。

公开(公告)号：US5210845A

公开(公告)日：1993-05-11

申请号：US618708

申请日：1990-11-28

申请人： John H. Crawford ,  Sundaravarathan R. Iyengar ,  James Nadir

发明人： John H. Crawford ,  Sundaravarathan R. Iyengar ,  James Nadir

IPC分类号： G06F12/08

CPC分类号： G06F12/0864 ,  G06F12/0884

摘要： A cache controller (10) which sits in parallel with a microprocessor bus (14, 15, 29) so as not to impede system response in the event of a cache miss. The cache controller tagram (24) is configured into a two ways, each way including tag and valid-bit storage for associatively searching the directory for cache data-array addresses. The external cache memory (8) is organized such that both ways are simultaneously available to a number of available memory modules in the system to thereby allow the way access time to occur in parallel with the tag lookup.

摘要翻译： 一个缓存控制器（10），其与微处理器总线（14,15,29）并联放置，以便在高速缓存未命中的情况下不妨碍系统响应。 高速缓存控制器tagram（24）被配置成两种方式，每种方式包括标签和有效位存储，用于将目录用于关联高速缓存数据阵列地址。 组织外部高速缓冲存储器（8）使得两种方式同时可用于系统中的多个可用存储器模块，从而允许与标签查找并行地进行访问时间。

公开(公告)号：US5173872A

公开(公告)日：1992-12-22

申请号：US73054

申请日：1987-07-13

申请人： John H. Crawford ,  Paul S. Ries

发明人： John H. Crawford ,  Paul S. Ries

IPC分类号： G06F12/10 ,  G06F12/14

CPC分类号： G06F12/1027 ,  G06F12/145

摘要： A content addressable memory (CAM) for use with a microprocessor allows comparison of the contents of the memory with input data. The CAM further allows certain bits of input data to be ignored from comparison. This feature allows certain bits, such as a bit indicating whether read or write access is allowed to certain information, to be ignored when the system is, for example, in a supervisory mode. Also disclosed is a method of precharging a hit line, which indicates whether or not a match was found in memory during the comparison, in order to increase the speed of the comparison process.

摘要翻译： 与微处理器一起使用的内容可寻址存储器（CAM）允许将存储器的内容与输入数据进行比较。 CAM进一步允许从比较中忽略输入数据的某些位。 该功能允许在系统例如处于监控模式时忽略诸如指示是否允许读取或写入访问某些信息的某些位。 还公开了一种对比较过程中指示是否在存储器中发现匹配的命中行的预充电方法，以便提高比较处理的速度。

公开(公告)号：US20150169026A1

公开(公告)日：2015-06-18

申请号：US13976817

申请日：2012-05-17

申请人： Devadatta V. Bodas ,  John H. Crawford ,  Alan G Gara

发明人： Devadatta V. Bodas ,  John H. Crawford ,  Alan G Gara

IPC分类号： G06F1/32

CPC分类号： G06F1/3206 ,  G06F1/3209 ,  G06F1/3234

摘要： A method and system for managing power consumption and performance of computing systems are described herein. The method includes monitoring an overall power consumption of the computing systems to determine whether the overall power consumption is above or below an overall power consumption limit, and monitoring a performance of each computing system to determine whether the performance is within a performance tolerance. The method further includes adjusting the power consumption limits for the computing systems or the performances of the computing systems such that the overall power consumption is below the overall power consumption limit and the performance of each computing system is within the performance tolerance.

摘要翻译： 本文描述了用于管理计算系统的功耗和性能的方法和系统。 该方法包括监视计算系统的总体功耗以确定总功耗是否高于或低于整体功耗限制，以及监视每个计算系统的性能以确定性能是否在性能容差内。 该方法还包括调整计算系统的功耗限制或计算系统的性能，使得总体功耗低于总功耗限制，并且每个计算系统的性能在性能容限内。