公开(公告)号：US06199118B1

公开(公告)日：2001-03-06

申请号：US09135703

申请日：1998-08-18

申请人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

发明人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

IPC分类号： G06F300

CPC分类号： G06F13/404 ,  G06F12/0879

摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective busses and further includes a plurality of queues placed within address and data paths linking the various controllers. A processor controller coupled between a processor local bus determines if an address forwarded from the processor is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If the address (i.e., target address) is not the first address (initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. Quad words are received in sequential order and placed into the queue. When the quad words are sent to the CPU, they are in toggle order. This ensures the processor controller, and eventually the processor, will read quad words in toggle mode address order, even though the quad words are dispatched from the peripheral device in address-increasing (non-toggle mode) order.

摘要翻译： 提供一种具有耦合在CPU总线，PCI总线和/或图形总线之间的总线接口单元的计算机。 总线接口单元包括链接到相应总线的控制器，还包括放置在连接各种控制器的地址和数据路径内的多个队列。 耦合在处理器本地总线之间的处理器控制器确定从处理器转发的地址是否是用于选择构成高速缓存行的四字组的地址序列中的第一地址。 如果地址（即，目标地址）不是该序列中的第一个地址（初始地址），则修改目标地址，使其成为该序列中的初始地址。 四个字按顺序接收并放入队列。 当四位字被发送到CPU时，它们处于切换顺序。 这确保处理器控制器，最终处理器将以切换模式地址顺序读取四个字，即使以寻址增加（非切换模式）顺序从外围设备发送四个字。

公开(公告)号：US06249847B1

公开(公告)日：2001-06-19

申请号：US09134057

申请日：1998-08-14

申请人： Kenneth T. Chin ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Michael J. Collins

发明人： Kenneth T. Chin ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Michael J. Collins

IPC分类号： G06F1378

CPC分类号： G06F13/18

摘要： A computer system that includes a CPU, a memory and a memory controller for controlling access to the memory. The memory controller generally includes arbitration logic for deciding which memory request among one or more pending requests should win arbitration. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to a clock signal and an arbitration enable signal. The synchronizing logic includes an AND gate and a latch for synchronizing the won signals. The memory controller also asynchronously arbitrates a second group of memory requests by asserting a won signal associated with the second group requests that is not synchronized to the clock signal. In this manner, the won signals for the second group of requests can be asserted earlier than the synchronized won signals, thereby permitting the asynchronously arbitrated second group memory requests to be performed earlier than otherwise possible.

摘要翻译： 一种包括CPU，存储器和用于控制对存储器的访问的存储器控​​制器的计算机系统。 存储器控制器通常包括仲裁逻辑，用于决定一个或多个待处理请求中哪个存储器请求应该赢得仲裁。 当请求赢得仲裁时，仲裁逻辑确定与该存储器请求对应的“赢”信号。 存储器控制器还包括同步逻辑，以将与第一组请求相对应的存储器请求同步到仲裁到时钟信号和仲裁使能信号。 同步逻辑包括与门和用于使获胜信号同步的锁存器。 存储器控制器还通过断言与不与时钟信号同步的第二组请求相关联的获胜信号来异步地仲裁第二组存储器请求。 以这种方式，第二组请求的获胜信号可以早于同步的获胜信号被断言，从而允许异步仲裁的第二组存储器请求比其他可能的更早执行。

公开(公告)号：US06961800B2

公开(公告)日：2005-11-01

申请号：US09967155

申请日：2001-09-28

申请人： Robert A. Lester ,  Kenneth T. Chin ,  Jim Blocker ,  John E. Larson ,  Phillip M. Jones ,  Paul B. Rawlins

发明人： Robert A. Lester ,  Kenneth T. Chin ,  Jim Blocker ,  John E. Larson ,  Phillip M. Jones ,  Paul B. Rawlins

IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/36

CPC分类号： G06F13/1657

摘要： Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

摘要翻译： 提高处理器性能的方法。 具体地，通过减少主机控制器内的一些延迟周期，可以提高请求处理速度。 用于提高处理速度的一种技术涉及在从存储器控制器获得数据之前发起延迟回复事务。 第二种技术涉及预期从块下一个请求（BNR）状态转换到总线优先级请求（BPRI）状态的需要，从而消除了等待请求检查以确定是否必须实现BPRI状态的需要。

公开(公告)号：US06275885B1

公开(公告)日：2001-08-14

申请号：US09164191

申请日：1998-09-30

申请人： Kenneth T. Chin ,  Michael J. Collins ,  John E. Larson ,  Robert A. Lester

发明人： Kenneth T. Chin ,  Michael J. Collins ,  John E. Larson ,  Robert A. Lester

IPC分类号： G06F1300

CPC分类号： G06F12/0831 ,  G06F13/16

摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit. Accordingly, the bus interface unit keeps CPU-derived cycles off the CPU bus to ensure memory arbiter grants ownership to a write cycle from the peripheral bus. In this fashion, data from the peripheral bus can be stored in system memory before accessing that data by a CPU read cycle. The number of snoop cycles which the bus interface unit can initiate is determined by configuration registers programmed during power on, reset or boot up of computer.

摘要翻译： 提供一种计算机，其具有耦合在CPU总线，外围总线（即PCI总线和/或图形总线）之间的总线接口单元和存储器总线。 总线接口单元包括链接到相应总线的控制器，以及放置在各种控制器之间的地址和数据路径内的多个队列。 外设总线控制器可以将写周期解码为存储器，然后处理器控制器可以请求并授予CPU本地总线的所有权。 然后可以窥探写周期的地址，以确定CPU高速缓存存储位置中是否存在有效数据。 如果是这样，可以进行回写操作。 CPU总线的所有权在侦听操作期间由总线接口单元维护，以及通过外设来源的写周期在写回和存储器总线的请求期间保持。 直到存储器总线的所有权由总线接口单元终止主存的存储器仲裁器才被授予。 因此，总线接口单元将CPU派生的周期从CPU总线保持，以确保存储器仲裁器将所有权授予来自外设总线的写周期。 以这种方式，通过CPU读取周期访问该数据之前，来自外围总线的数据可以存储在系统存储器中。 总线接口单元可以启动的窥探周期数由计算机上电，复位或启动时编程的配置寄存器决定。

公开(公告)号：US07120758B2

公开(公告)日：2006-10-10

申请号：US10365018

申请日：2003-02-12

申请人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

发明人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

IPC分类号： G06F12/00 ,  G06F3/00

CPC分类号： G06F13/1673

摘要： Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

摘要翻译： 提高处理器性能的方法和装置。 在一些实施例中，可以通过在初始请求期间通过后续请求重用存储在缓冲器中的数据来改善处理速度。 控制器中的临时存储缓冲区的分配可以做出以允许数据重用的潜力。 此外，可以指定热缓冲器以允许重新使用存储在热缓冲器中的数据。 在随后的请求中，存储在热缓冲器中的数据可以被发送到请求设备而不从存储器重新检索数据。

公开(公告)号：US06823424B2

公开(公告)日：2004-11-23

申请号：US09966666

申请日：2001-09-28

申请人： John E. Larson ,  Robert A. Lester ,  Elizabeth A. Richard

发明人： John E. Larson ,  Robert A. Lester ,  Elizabeth A. Richard

IPC分类号： G06F1300

CPC分类号： G06F11/1076 ,  G06F2211/1088 ,  G11C29/52

摘要： A technique for selecting events associated with a hot-plug operation. More specifically, a programmable configuration register may be used to provide a mechanism for periodically scheduling requests associated with a hot-plug operation, such as initialization, rebuild, and verify requests. An arbiter is provided to facilitate an ordered access to a memory system. A user can select a periodic interval such that hot-plug requests are periodically executed during the execution of normal requests through the arbiter. The user-selectable interval may be dependent on the specific application of the system and the importance of operating in a redundant mode.

摘要翻译： 用于选择与热插拔操作相关联的事件的技术。 更具体地，可编程配置寄存器可用于提供用于周期性地调度与诸如初始化，重建和验证请求之类的热插拔操作相关联的请求的机制。 提供仲裁器以便于有序访问存储器系统。 用户可以选择周期性间隔，使得在通过仲裁器执行正常请求期间热插拔请求被周期性地执行。 用户可选择的间隔可以取决于系统的具体应用和以冗余模式操作的重要性。

公开(公告)号：US5774680A

公开(公告)日：1998-06-30

申请号：US570394

申请日：1995-12-11

申请人： Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

发明人： Christopher C. Wanner ,  Jeffrey C. Stevens ,  Robert A. Lester ,  Dwight D. Riley ,  David J. Maguire ,  James Edwards

IPC分类号： G06F13/12 ,  G06F13/28 ,  G06F13/00

CPC分类号： G06F13/28 ,  G06F13/126

摘要： A computer system having separate, yet compatible DMA controllers on a bus. Each DMA controller for controlling at least one DMA channel, each DMA controller having an independent set of registers for performing DMA operations and a configuration register for indicating channel status and designation. A DMA master for compatibly communicating with a processor and for initializing and communicating with the multiple DMA controllers.

公开(公告)号：US5731550A

公开(公告)日：1998-03-24

申请号：US813922

申请日：1997-03-07

申请人： Robert A. Lester ,  Paul Junghans

发明人： Robert A. Lester ,  Paul Junghans

IPC分类号： B06B1/06 ,  G01V1/52 ,  G01V1/40

CPC分类号： B06B1/0603 ,  G01V1/523 ,  Y10S367/911

摘要： A dipole acoustic well logging instrument including an acoustic transmitter. Receiver sections are disposed at axially spaced apart locations from the acoustic transmitter. Each receiver section includes an outer shoulder at each end adapted to be placed in acoustically isolated contact with an internal shoulder of a connector coupling when the instrument is in tension. The outer shoulders have an acoustically isolating material disposed on their surfaces. The receiver sections include an inner shoulder at each end adapted to be placed in direct contact with an external shoulder of the connector coupling when the instrument is in compression. The instrument includes one connector couplings disposed at each end of each receiver section to couple the receiver sections to each other and to the remainder of the instrument. At least one receiver element is disposed in a passage formed into each of the receiver sections. In one embodiment of the invention, the receiver element can be a bimorph-type dipole acoustic sensor. In another embodiment, the receiver element can be formed from a plurality of radially spaced apart piezoelectric elements.

摘要翻译： 包括声发射器的偶极声测井仪器。 接收器部分设置在离声发射器的轴向间隔开的位置处。 每个接收器部分包括在每个端部处的外肩部，其适于在器械处于张力时与连接器联接器的内部肩部放置在声隔离接触中。 外肩部具有设置在其表面上的隔音材料。 接收器部分包括在每个端部处的内肩部，其适于在仪器处于压缩状态时与连接器联接器的外肩部直接接触。 仪器包括设置在每个接收器部分的每个端部处的一个连接器联接器，以将接收器部分彼此连接并连接到仪器的其余部分。 至少一个接收器元件设置在形成每个接收器部分的通道中。 在本发明的一个实施例中，接收器元件可以是双压电晶片型偶极子声学传感器。 在另一个实施例中，接收器元件可以由多个径向隔开的压电元件形成。

公开(公告)号：US4893285A

公开(公告)日：1990-01-09

申请号：US195443

申请日：1988-05-12

申请人： Jean P. H. R. M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

发明人： Jean P. H. R. M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

IPC分类号： E21B47/00 ,  G01V1/44

CPC分类号： E21B47/0005 ,  G01V1/44

摘要： In accordance with principles of the present invention methods and apparatus are provided for evaluating the quality of the cement bond in cased boreholes. Acoustic energy is used to excite the borehole-casing-annulus-formation system and the quality of the cement bond is determined by examining the ratios of the signals received by two longitudinally spaced apart receivers supported on a sonde. The acoustic energy is generated by two transmitters symmetrically disposed above and below the receivers along the sonde. The spacings between the receivers themselves and between the receivers and the transmitters are selected so as to enhance the correlation between the ratios of the received signals and the quality of the cement bond log. An additional receiver, supported on the sonde at a small distance from one of the transmitters, is employed to determine the quality of the cement bond in hard formations.

摘要翻译： 根据本发明的原理，提供了用于评估套管钻孔中的水泥粘合剂的质量的方法和装置。 声能被用于激发钻孔套管 - 环空形成系统，并且通过检查由主体上支撑的两个纵向间隔开的接收器接收的信号的比率来确定水泥接合质量。 声能由对称设置在探头的接收器上方和下方的两个发射器产生。 选择接收器本身之间以及接收器和发射器之间的间隔，以便增强接收信号的比率与水泥结合记录的质量之间的相关性。 使用一个额外的接收器，在距离其中一个发射器的距离较小的位置上在主探头上支撑，用于确定硬地层中水泥粘结的质量。

公开(公告)号：US4757479A

公开(公告)日：1988-07-12

申请号：US394395

申请日：1982-07-01

申请人： Jean-Pierre H.R.M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

发明人： Jean-Pierre H.R.M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

IPC分类号： E21B47/00 ,  G01V1/44 ,  G01V1/40

CPC分类号： E21B47/0005 ,  G01V1/44

摘要： In accordance with principles of the present invention methods and apparatus are provided for evaluating the quality of the cement bond in cased boreholes. Acoustic energy is used to excite the borehole-casing-annulus-formation system and the quality of the cement bond is determined by examining the ratios of the signals received by two longitudinally spaced apart receivers supported on a sonde. The acoustic energy is generated by two transmitters symmetrically disposed above and below the receivers along the sonde. The spacings between the receivers themselves and between the receivers and the transmitters are selected so as to enhance the correlation between the ratios of the received signals and the quality of the cement bond log. An additional receiver, supported on the sonde at a small distance from one of the transmitters, is employed to determine the quality of the cement bond in hard formations.

摘要翻译： 根据本发明的原理，提供了用于评估套管钻孔中的水泥粘合剂的质量的方法和装置。 声能被用于激发钻孔套管 - 环空形成系统，并且通过检查由主体上支撑的两个纵向间隔开的接收器接收的信号的比率来确定水泥接合质量。 声能由对称设置在探头的接收器上方和下方的两个发射器产生。 选择接收器本身之间以及接收器和发射器之间的间隔，以便增强接收信号的比率与水泥结合记录的质量之间的相关性。 使用一个额外的接收器，在距离其中一个发射器的距离较小的位置上在主探头上支撑，用于确定硬地层中水泥粘结的质量。