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    Technique for improving processor performance
    1.
    发明授权
    Technique for improving processor performance 失效
    提高处理器性能的技术

    公开(公告)号：US07120758B2

    公开(公告)日：2006-10-10

    申请号：US10365018

    申请日：2003-02-12

    申请人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

    发明人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

    IPC分类号： G06F12/00 ,  G06F3/00

    CPC分类号： G06F13/1673

    摘要： Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

    摘要翻译： 提高处理器性能的方法和装置。 在一些实施例中，可以通过在初始请求期间通过后续请求重用存储在缓冲器中的数据来改善处理速度。 控制器中的临时存储缓冲区的分配可以做出以允许数据重用的潜力。 此外，可以指定热缓冲器以允许重新使用存储在热缓冲器中的数据。 在随后的请求中，存储在热缓冲器中的数据可以被发送到请求设备而不从存储器重新检索数据。

    Method for improving processor performance
    2.
    发明授权
    Method for improving processor performance 失效
    提高处理器性能的方法

    公开(公告)号：US06961800B2

    公开(公告)日：2005-11-01

    申请号：US09967155

    申请日：2001-09-28

    申请人： Robert A. Lester ,  Kenneth T. Chin ,  Jim Blocker ,  John E. Larson ,  Phillip M. Jones ,  Paul B. Rawlins

    发明人： Robert A. Lester ,  Kenneth T. Chin ,  Jim Blocker ,  John E. Larson ,  Phillip M. Jones ,  Paul B. Rawlins

    IPC分类号： G06F13/00 ,  G06F13/16 ,  G06F13/36

    CPC分类号： G06F13/1657

    摘要： Methods for improving processor performance. Specifically, by reducing some of the latency cycles within a host controller, request processing speed can be improved. One technique for improving processing speed involves initiating a deferred reply transaction before the data is available from a memory controller. A second technique involves anticipating the need to transition from a block next request (BNR) state to a bus priority request (BPRI) state, thereby eliminating the need to wait for a request check to determine if the BPRI state must be implemented.

    摘要翻译： 提高处理器性能的方法。 具体地，通过减少主机控制器内的一些延迟周期，可以提高请求处理速度。 用于提高处理速度的一种技术涉及在从存储器控制器获得数据之前发起延迟回复事务。 第二种技术涉及预期从块下一个请求（BNR）状态转换到总线优先级请求（BPRI）状态的需要，从而消除了等待请求检查以确定是否必须实现BPRI状态的需要。

    Memory controller including write posting queues, bus read control logic, and a data contents counter
    3.
    发明授权
    Memory controller including write posting queues, bus read control logic, and a data contents counter 失效
    存储器控制器包括写入寄存队列，总线读取控制逻辑和数据内容计数器

    公开(公告)号：US5938739A

    公开(公告)日：1999-08-17

    申请号：US811587

    申请日：1997-03-05

    申请人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

    发明人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

    IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00 ,  G06F13/14

    CPC分类号： G06F12/0831 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1694

    摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

    摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。

    System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation
    4.
    发明授权
    System having a plurality of posting queues associated with different types of write operations for selectively checking one queue based upon type of read operation 失效
    具有与不同类型的写入操作相关联的多个发布队列的系统，用于基于读取操作的类型选择性地检查一个队列

    公开(公告)号：US5634073A

    公开(公告)日：1997-05-27

    申请号：US324246

    申请日：1994-10-14

    申请人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

    发明人： Michael J. Collins ,  Gary W. Thome ,  Michael P. Moriarty ,  Jens K. Ramsey ,  John E. Larson

    IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/00

    CPC分类号： G06F12/0831 ,  G06F13/1605 ,  G06F13/1642 ,  G06F13/1694

    摘要： A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices. The memory controller includes a plurality of registers that specify number of clock periods for the particular portions of a conventional DRAM cycle which are used to control state machine operations.

    摘要翻译： 存储器控制器，其在处理器和PCI总线与存储器系统之间提供一系列队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 内容可寻址存储器（CAM）被用作PCI到存储器队列。 当处理器执行读取请求时，检查CAM以确定PCI到存储器队列中的待处理写入操作之一是否与处理器的读取操作相同。 如果是这样，则在PCI存储器队列清除写入之前，不执行读取操作。 为了解决中止“内存读取多个”操作的问题，接收到来自PCI总线接口的中断信号，并且尽快完成读取前一周期，即使前面的读取周期尚未完全完成。 存储器控制器基于该周期是来自处理器还是来自PCI总线来改进预测规则，以在使用PCI总线周期时允许更有效的预充电。 存储器控制器是高度可编程的，适用于多种速度和类型的处理器和几种存储器件的速度。 存储器控制器包括多个寄存器，其指定用于控制状态机操作的常规DRAM周期的特定部分的时钟周期数。

    Computer system controller and method with processor write posting hold off on PCI master memory request
    5.
    发明授权
    Computer system controller and method with processor write posting hold off on PCI master memory request 失效
    具有处理器写入寄存功能的计算机系统控制器和方法在PCI主存储器请求中保持不变

    公开(公告)号：US06209067B1

    公开(公告)日：2001-03-27

    申请号：US08566514

    申请日：1995-12-04

    申请人： Michael J. Collins ,  Michael P. Moriarty ,  John E. Larson ,  Jens K. Ramsey

    发明人： Michael J. Collins ,  Michael P. Moriarty ,  John E. Larson ,  Jens K. Ramsey

    IPC分类号： G06F1336

    CPC分类号： G06F13/1605 ,  G06F12/0831 ,  G06F13/1642 ,  G06F13/1694

    摘要： A computer system including a memory controller provides a series of queues between a processor and a peripheral component interconnect (PCI) bus and a memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A write posting queue for processor to PCI writes must be flushed before a PCI device can access memory. If the queue is not empty when the PCI device requests a memory read, the PCI device is forced to retry the operation while the write posting queue is flushed. Also, while the queue is flushed, the processor is prevented from further posting to the queue. A timer provides a further temporary time that the processor is precluded from posting to allow enough time for the PCI master to retry the operation.

    摘要翻译： 包括存储器控制器的计算机系统在处理器与外围部件互连（PCI）总线和存储器系统之间提供一系列的队列。 内存一致性以两种不同的方式保持。 在PCI总线接受任何读操作之前，两个发送队列都必须为空。 在PCI设备可以访问内存之前，必须刷新处理器到PCI写入的写入队列。 如果PCI设备请求存储器读取队列不为空，则在刷新写入过帐队列时，强制PCI设备重试该操作。 此外，当刷新队列时，防止处理器进一步发布到队列。 定时器提供进一步的临时时间，使处理器不被发布以允许足够的时间使PCI主机重试该操作。

    Memory data verify operation
    10.
    发明授权
    Memory data verify operation 有权
    内存数据验证操作

    公开(公告)号：US06715116B2

    公开(公告)日：2004-03-30

    申请号：US09769958

    申请日：2001-01-25

    申请人： Robert A. Lester ,  John M. MacLaren ,  Patrick L. Ferguson ,  John E. Larson

    发明人： Robert A. Lester ,  John M. MacLaren ,  Patrick L. Ferguson ,  John E. Larson

    IPC分类号： G11C2900

    CPC分类号： G06F11/1076 ,  G06F2211/1088 ,  G11C29/52

    摘要： A system and technique for detecting data errors in a memory device. More specifically, data errors in a memory device are detected by initiating an internal READ command or verify operation from a set of logic which is internal to the memory system in which the memory devices reside. Rather than relying on a READ command to be issued from an external device, via a host controller, the verify logic initiates verify routine in response to an event such as an operator instruction, hot-plug operation, or a periodic schedule. By implementing the verify operation, the system does not rely on external READ commands to verify data integrity. The verify routine may rely on typical ECC error logging mechanisms and may be used in a RAID memory architecture. Further, the verify routine may be used in conjunction with other error logging and correction logic, as well as scrubbing logic.

    摘要翻译： 一种用于检测存储器件中的数据错误的系统和技术。 更具体地，通过从存储器设备所在的存储器系统内部的一组逻辑启动内部READ命令或验证操作来检测存储器设备中的数据错误。 验证逻辑不是依赖于通过主机控制器从外部设备发出READ命令，而是响应诸如操作员指令，热插拔操作或周期性调度的事件来启动验证程序。 通过实施验证操作，系统不依赖外部READ命令来验证数据完整性。 验证例程可能依赖于典型的ECC错误记录机制，并可用于RAID存储器架构。 此外，验证程序可以与其他错误记录和校正逻辑以及擦洗逻辑结合使用。