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44 条记录 (耗时 0.039 秒)

    Acoustic dipole well logging instrument
    1.
    发明授权
    Acoustic dipole well logging instrument 失效
    声学双极测井仪

    公开(公告)号：US5731550A

    公开(公告)日：1998-03-24

    申请号：US813922

    申请日：1997-03-07

    申请人： Robert A. Lester ,  Paul Junghans

    发明人： Robert A. Lester ,  Paul Junghans

    IPC分类号： B06B1/06 ,  G01V1/52 ,  G01V1/40

    CPC分类号： B06B1/0603 ,  G01V1/523 ,  Y10S367/911

    摘要： A dipole acoustic well logging instrument including an acoustic transmitter. Receiver sections are disposed at axially spaced apart locations from the acoustic transmitter. Each receiver section includes an outer shoulder at each end adapted to be placed in acoustically isolated contact with an internal shoulder of a connector coupling when the instrument is in tension. The outer shoulders have an acoustically isolating material disposed on their surfaces. The receiver sections include an inner shoulder at each end adapted to be placed in direct contact with an external shoulder of the connector coupling when the instrument is in compression. The instrument includes one connector couplings disposed at each end of each receiver section to couple the receiver sections to each other and to the remainder of the instrument. At least one receiver element is disposed in a passage formed into each of the receiver sections. In one embodiment of the invention, the receiver element can be a bimorph-type dipole acoustic sensor. In another embodiment, the receiver element can be formed from a plurality of radially spaced apart piezoelectric elements.

    摘要翻译： 包括声发射器的偶极声测井仪器。 接收器部分设置在离声发射器的轴向间隔开的位置处。 每个接收器部分包括在每个端部处的外肩部，其适于在器械处于张力时与连接器联接器的内部肩部放置在声隔离接触中。 外肩部具有设置在其表面上的隔音材料。 接收器部分包括在每个端部处的内肩部，其适于在仪器处于压缩状态时与连接器联接器的外肩部直接接触。 仪器包括设置在每个接收器部分的每个端部处的一个连接器联接器，以将接收器部分彼此连接并连接到仪器的其余部分。 至少一个接收器元件设置在形成每个接收器部分的通道中。 在本发明的一个实施例中，接收器元件可以是双压电晶片型偶极子声学传感器。 在另一个实施例中，接收器元件可以由多个径向隔开的压电元件形成。

    Computer system with synchronous memory arbiter that permits asynchronous memory requests
    3.
    发明授权
    Computer system with synchronous memory arbiter that permits asynchronous memory requests 有权
    具有允许异步存储器请求的同步存储器仲裁器的计算机系统

    公开(公告)号：US06249847B1

    公开(公告)日：2001-06-19

    申请号：US09134057

    申请日：1998-08-14

    申请人： Kenneth T. Chin ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Michael J. Collins

    发明人： Kenneth T. Chin ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo ,  Michael J. Collins

    IPC分类号： G06F1378

    CPC分类号： G06F13/18

    摘要： A computer system that includes a CPU, a memory and a memory controller for controlling access to the memory. The memory controller generally includes arbitration logic for deciding which memory request among one or more pending requests should win arbitration. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to a clock signal and an arbitration enable signal. The synchronizing logic includes an AND gate and a latch for synchronizing the won signals. The memory controller also asynchronously arbitrates a second group of memory requests by asserting a won signal associated with the second group requests that is not synchronized to the clock signal. In this manner, the won signals for the second group of requests can be asserted earlier than the synchronized won signals, thereby permitting the asynchronously arbitrated second group memory requests to be performed earlier than otherwise possible.

    摘要翻译： 一种包括CPU，存储器和用于控制对存储器的访问的存储器控​​制器的计算机系统。 存储器控制器通常包括仲裁逻辑，用于决定一个或多个待处理请求中哪个存储器请求应该赢得仲裁。 当请求赢得仲裁时，仲裁逻辑确定与该存储器请求对应的“赢”信号。 存储器控制器还包括同步逻辑，以将与第一组请求相对应的存储器请求同步到仲裁到时钟信号和仲裁使能信号。 同步逻辑包括与门和用于使获胜信号同步的锁存器。 存储器控制器还通过断言与不与时钟信号同步的第二组请求相关联的获胜信号来异步地仲裁第二组存储器请求。 以这种方式，第二组请求的获胜信号可以早于同步的获胜信号被断言，从而允许异步仲裁的第二组存储器请求比其他可能的更早执行。

    Method and apparatus for cement bond tool
    5.
    发明授权
    Method and apparatus for cement bond tool 失效
    水泥粘合工具的方法和装置

    公开(公告)号：US4893285A

    公开(公告)日：1990-01-09

    申请号：US195443

    申请日：1988-05-12

    申请人： Jean P. H. R. M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

    发明人： Jean P. H. R. M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

    IPC分类号： E21B47/00 ,  G01V1/44

    CPC分类号： E21B47/0005 ,  G01V1/44

    摘要： In accordance with principles of the present invention methods and apparatus are provided for evaluating the quality of the cement bond in cased boreholes. Acoustic energy is used to excite the borehole-casing-annulus-formation system and the quality of the cement bond is determined by examining the ratios of the signals received by two longitudinally spaced apart receivers supported on a sonde. The acoustic energy is generated by two transmitters symmetrically disposed above and below the receivers along the sonde. The spacings between the receivers themselves and between the receivers and the transmitters are selected so as to enhance the correlation between the ratios of the received signals and the quality of the cement bond log. An additional receiver, supported on the sonde at a small distance from one of the transmitters, is employed to determine the quality of the cement bond in hard formations.

    摘要翻译： 根据本发明的原理，提供了用于评估套管钻孔中的水泥粘合剂的质量的方法和装置。 声能被用于激发钻孔套管 - 环空形成系统，并且通过检查由主体上支撑的两个纵向间隔开的接收器接收的信号的比率来确定水泥接合质量。 声能由对称设置在探头的接收器上方和下方的两个发射器产生。 选择接收器本身之间以及接收器和发射器之间的间隔，以便增强接收信号的比率与水泥结合记录的质量之间的相关性。 使用一个额外的接收器，在距离其中一个发射器的距离较小的位置上在主探头上支撑，用于确定硬地层中水泥粘结的质量。

    Method and apparatus for cement bond logging
    6.
    发明授权
    Method and apparatus for cement bond logging 失效
    水泥债券采伐方法和装置

    公开(公告)号：US4757479A

    公开(公告)日：1988-07-12

    申请号：US394395

    申请日：1982-07-01

    申请人： Jean-Pierre H.R.M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

    发明人： Jean-Pierre H.R.M. Masson ,  Lee H. Gollwitzer ,  Robert A. Lester

    IPC分类号： E21B47/00 ,  G01V1/44 ,  G01V1/40

    CPC分类号： E21B47/0005 ,  G01V1/44

    摘要： In accordance with principles of the present invention methods and apparatus are provided for evaluating the quality of the cement bond in cased boreholes. Acoustic energy is used to excite the borehole-casing-annulus-formation system and the quality of the cement bond is determined by examining the ratios of the signals received by two longitudinally spaced apart receivers supported on a sonde. The acoustic energy is generated by two transmitters symmetrically disposed above and below the receivers along the sonde. The spacings between the receivers themselves and between the receivers and the transmitters are selected so as to enhance the correlation between the ratios of the received signals and the quality of the cement bond log. An additional receiver, supported on the sonde at a small distance from one of the transmitters, is employed to determine the quality of the cement bond in hard formations.

    摘要翻译： 根据本发明的原理，提供了用于评估套管钻孔中的水泥粘合剂的质量的方法和装置。 声能被用于激发钻孔套管 - 环空形成系统，并且通过检查由主体上支撑的两个纵向间隔开的接收器接收的信号的比率来确定水泥接合质量。 声能由对称设置在探头的接收器上方和下方的两个发射器产生。 选择接收器本身之间以及接收器和发射器之间的间隔，以便增强接收信号的比率与水泥结合记录的质量之间的相关性。 使用一个额外的接收器，在距离其中一个发射器的距离较小的位置上在主探头上支撑，用于确定硬地层中水泥粘结的质量。

    Technique for improving processor performance
    7.
    发明授权
    Technique for improving processor performance 失效
    提高处理器性能的技术

    公开(公告)号：US07120758B2

    公开(公告)日：2006-10-10

    申请号：US10365018

    申请日：2003-02-12

    申请人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

    发明人： Phillip M. Jones ,  Robert A. Lester ,  Jens K. Ramsey ,  William J. Walker ,  John E. Larson ,  James Andre ,  Paul Rawlins

    IPC分类号： G06F12/00 ,  G06F3/00

    CPC分类号： G06F13/1673

    摘要： Method and apparatus for improving processor performance. In some embodiments, processing speed may be improved by reusing data stored in a buffer during an initial request by subsequent requests. Assignment of temporary storage buffers in a controller may be made to allow for the potential for reuse of the data. Further, a hot buffer may be designated to allow for reuse of the data stored in the hot buffer. On subsequent requests, data stored in the hot buffer may be sent to a requesting device without re-retrieving the data from memory.

    摘要翻译： 提高处理器性能的方法和装置。 在一些实施例中，可以通过在初始请求期间通过后续请求重用存储在缓冲器中的数据来改善处理速度。 控制器中的临时存储缓冲区的分配可以做出以允许数据重用的潜力。 此外，可以指定热缓冲器以允许重新使用存储在热缓冲器中的数据。 在随后的请求中，存储在热缓冲器中的数据可以被发送到请求设备而不从存储器重新检索数据。

    Hot-upgrade/hot-add memory
    8.
    发明授权
    Hot-upgrade/hot-add memory 失效
    热升级/热添加内存

    公开(公告)号：US06854070B2

    公开(公告)日：2005-02-08

    申请号：US09769978

    申请日：2001-01-25

    申请人： Jerome J. Johnson ,  John M. MacLaren ,  Robert A. Lester ,  John E. Larson ,  Gary J. Piccirillo ,  Christian H. Post ,  Jeffery Galloway ,  Ho M. Lai ,  Anisha Anand ,  Eric Rose

    发明人： Jerome J. Johnson ,  John M. MacLaren ,  Robert A. Lester ,  John E. Larson ,  Gary J. Piccirillo ,  Christian H. Post ,  Jeffery Galloway ,  Ho M. Lai ,  Anisha Anand ,  Eric Rose

    IPC分类号： G06F11/10 ,  G06F11/00

    CPC分类号： G06F11/108

    摘要： A method of adding memory capacity to a computer system. The computer system comprises a redundant memory system including a plurality of memory cartridges. By powering-down a memory cartridge, adding an additional memory module to the memory cartridge, and powering-up the memory cartridge for each memory cartridge in the system, the system can transition from a redundant mode of operation to a non-redundant mode of operation for each power-down, thus allowing the computer system to remain functional during the addition of the memory module. Alternatively, memory cartridges with higher memory capacity than those currently present in the computer system can be used to replace existing memory cartridges in the computer system, using the same techniques.

    摘要翻译： 一种向计算机系统增加内存容量的方法。 计算机系统包括包括多个存储器盒的冗余存储器系统。 通过关闭存储卡，将额外的内存模块添加到内存盒，并为系统中的每个内存盒启动内存盒，系统可以从冗余操作模式转换到非冗余模式 操作每个掉电，从而允许计算机系统在添加存储器模块期间保持功能。 或者，可以使用具有比当前存在于计算机系统中的存储器容量更高的存储器盒来替代计算机系统中的现有存储器盒，使用相同的技术。

    System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus
    10.
    发明授权
    System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus 有权
    用于最佳延迟或重试一个周期的系统和方法，处理器总线上用于外设总线

    公开(公告)号：US06216190B1

    公开(公告)日：2001-04-10

    申请号：US09164192

    申请日：1998-09-30

    申请人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

    发明人： Kenneth T. Chin ,  Clarence K. Coffee ,  Michael J. Collins ,  Jerome J. Johnson ,  Phillip M. Jones ,  Robert A. Lester ,  Gary J. Piccirillo

    IPC分类号： G06F1342

    CPC分类号： G06F13/4239

    摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the CPU bus for controlling the transfer of cycles from the CPU to the peripheral bus and memory bus. Those cycles can be arranged in order within the CPU bus pipeline. A subset of cycles destined for a peripheral bus can be stalled within a snoop phase associated with the CPU bus. Snoop stall can continue until a memory cycle is encountered upon the CPU bus pipeline within a phase prior to the snoop phase. Once the memory cycle progresses to the snoop phase, snoop stall can be discontinued and the previous, peripheral cycles can then be deferred and/or retried, allowing the memory cycle to be quickly dispatched through all phases of the CPU bus and onto the memory bus. In this fashion, memory cycles can be completed quickly, yet deferrals or retries are minimized to avoid the throughput penalty associated with deferring or retrying cycles back again through each phase of the CPU bus.

    摘要翻译： 提供一种具有耦合在CPU总线，外围总线和存储器总线之间的总线接口单元的计算机。 总线接口单元包括连接到CPU总线的处理器控制器，用于控制从CPU到外围总线和存储器总线的周期传送。 这些循环可以顺序排列在CPU总线管道中。 在与CPU总线相关联的窥探阶段中，可能会停止发往外围总线的周期的子集。 在窥探阶段之前的一个阶段，在CPU总线流水线上，Snoop停止可以继续，直到遇到内存循环。 一旦存储器周期进行到窥探阶段，就可以停止侦听停止，然后可以延迟和/或重试先前的周边周期，从而允许通过CPU总线的所有阶段和存储器总线快速调度存储器周期 。 以这种方式，可以快速完成内存周期，但是延迟或重试最小化，以避免通过CPU总线的每个阶段再次延迟或重试周期相关的吞吐量损失。