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公开(公告)号：US08879571B2
公开(公告)日：2014-11-04
申请号：US13286878
申请日：2011-11-01
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
IPC分类号： G06F15/16 , H04L12/46 , H04L12/931
CPC分类号： H04L12/4633 , H04L49/505
摘要： Techniques for delays based on packet sizes are provided. Request messages may identify the size of a data packet. Delays may be initiated based in part on a portion of the size of the data packet. The delays may also be based in part on target issue intervals. Request messages may be sent after the delays.
摘要翻译： 提供了基于分组大小的延迟技术。 请求消息可以标识数据分组的大小。 可以部分地基于数据分组的大小的一部分来启动延迟。 这些延误也可能部分地基于目标问题间隔。 请求消息可能会在延迟之后发送。
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公开(公告)号：US08830838B2
公开(公告)日：2014-09-09
申请号：US13232645
申请日：2011-09-14
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
CPC分类号： H04L1/1607
摘要： Techniques described herein provide for sending data packets from source to destination nodes. Indicators, such as counters, may determine the configuration of node interfaces. The data packets may be sent based on a comparison of current and stored indicators.
摘要翻译： 本文描述的技术提供从源到目的地节点发送数据分组。 指示器，如计数器，可以确定节点接口的配置。 可以基于当前和存储的指示符的比较来发送数据分组。
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公开(公告)号：US20130250777A1
公开(公告)日：2013-09-26
申请号：US13430265
申请日：2012-03-26
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
CPC分类号： H04L43/10 , H04L43/106 , H04L43/12
摘要： Techniques are provided to trace packet descriptors. A received packet may be identified. A packet descriptor associated with the received packet may be created. A trace indicator in the packet descriptor may be set. The presence of a packet descriptor with the trace indicator set may be logged by a detector.
摘要翻译： 提供了跟踪数据包描述符的技术。 可以识别接收的分组。 可以创建与所接收的分组相关联的分组描述符。 可以设置分组描述符中的跟踪指示符。 具有跟踪指示器组的分组描述符的存在可以由检测器记录。
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公开(公告)号：US20120320910A1
公开(公告)日：2012-12-20
申请号：US13161894
申请日：2011-06-16
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
IPC分类号： H04L12/56
摘要： Techniques described herein provide for sending and receiving messages. The messages are associated with streams. Indicators associated with the streams determine if the messages are sent.
摘要翻译： 本文描述的技术提供了发送和接收消息。 消息与流相关联。 与流相关联的指示符确定消息是否被发送。
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公开(公告)号：US07346802B2
公开(公告)日：2008-03-18
申请号：US10769371
申请日：2004-01-30
申请人： Aland B. Adams , Michael L. Ziegler , Bo Quan , Scott Greenidge
发明人： Aland B. Adams , Michael L. Ziegler , Bo Quan , Scott Greenidge
IPC分类号： G06F11/00
CPC分类号： H04L45/00 , H04L29/12801 , H04L29/12858 , H04L29/12886 , H04L45/22 , H04L45/28 , H04L61/6004 , H04L61/6031 , H04L61/6045 , H04L67/1097
摘要： Systems, methods, and machine-readable media are disclosed for routing communications to a storage area network (SAN). In one embodiment, the machine-readable media includes first program code to determine a route path through a gateway to a SAN for each of a plurality of addresses of an interface of a server. The first program code determines the route path by applying an algorithm to one or more numerical values associated with the address. The machine-readable media includes second program code to configure the gateway with the route paths.
摘要翻译： 公开了用于将通信路由到存储区域网络（SAN）的系统，方法和机器可读介质。 在一个实施例中，机器可读介质包括第一程序代码，以确定通过服务器的接口的多个地址中的每一个的网关到SAN的路由路径。 第一程序代码通过将算法应用于与地址相关联的一个或多个数值来确定路线路径。 机器可读介质包括用于使用路由路径配置网关的第二程序代码。
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26.发明授权公开(公告)号：US06874138B1
公开(公告)日：2005-03-29
申请号：US09724616
申请日：2000-11-28
CPC分类号： G06F11/1438 , G06F11/1489
摘要： Method and apparatus for resuming execution of a failed computer program. A program is compiled using two compilers to generate first and second sets of object code. Checkpoints are identified in the program, and checkpoint code is generated for execution at the checkpoints. If execution of the first set of object code fails, checkpoint data is recovered and execution of the program is resumed using either the first or second set of object code. In one embodiment, the first set of object code is re-executed before trying the second set of object code.
摘要翻译： 恢复执行故障计算机程序的方法和装置。 使用两个编译器编译程序来生成第一组和第二组目标代码。 检查点在程序中标识，生成检查点代码以便在检查点执行。 如果第一组目标代码的执行失败，则检查点数据被恢复，并且使用第一组或第二组目标代码恢复程序的执行。 在一个实施例中，在尝试第二组目标代码之前重新执行第一组目标代码。
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公开(公告)号：US06473845B1
公开(公告)日：2002-10-29
申请号：US09675021
申请日：2000-09-28
IPC分类号： G06F1300
CPC分类号： G06F12/0292 , G06F13/1663
摘要： In general, a system and method is provided for dynamically reallocating computer memory. A mapper receives requests to access data. The requests include bus addresses, and the mapper maps the bus addresses to memory unit addresses based on a plurality of mappings maintained by the mapper. The memory unit addresses identify a plurality of memory locations including a destination memory location and a source memory location. Data requested by the requests received by the mapper is accessed based on the memory unit addresses mapped from the bus addresses included in the requests. When desired, a data value from the source memory location is dynamically moved to the destination memory location, and the mappings are updated such that a bus address mapped to a memory unit address identifying the source memory location is instead mapped to a memory unit address identifying the destination memory location.
摘要翻译： 通常，提供用于动态地重新分配计算机存储器的系统和方法。 映射器接收访问数据的请求。 请求包括总线地址，并且映射器基于由映射器维护的多个映射将总线地址映射到存储器单元地址。 存储器单元地址识别包括目的地存储器位置和源存储器位置的多个存储器位置。 基于从请求中包括的总线地址映射的存储器单元地址来访问由映射器接收到的请求所请求的数据。 当需要时，来自源存储器位置的数据值被动态地移动到目的地存储器位置，并且映射被更新，使得映射到标识源存储器位置的存储器单元地址的总线地址被映射到存储器单元地址识别 目的地记忆位置。
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公开(公告)号：US4398243A
公开(公告)日：1983-08-09
申请号：US143651
申请日：1980-04-25
IPC分类号： G06F9/26 , G06F9/30 , G06F11/10 , G06F11/14 , G06F12/02 , G06F12/06 , G06F12/08 , G06F12/10 , G06F12/14
CPC分类号： G06F9/342 , G06F11/10 , G06F11/14 , G06F12/0292 , G06F12/0802 , G06F12/1009 , G06F12/14 , G06F9/26 , G06F9/30 , G06F11/106 , G06F12/0623
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different level of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
摘要翻译： 一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。 该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。 解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。 该系统使用八个存储段（环）的分层存储器存储，根据不同的权限级别以特权方式访问环。 存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。
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公开(公告)号：US4386399A
公开(公告)日：1983-05-31
申请号：US143561
申请日：1980-04-25
申请人： Edward Rasala , Steven Wallach , Carl J. Alsing , Kenneth D. Holberger , Charles J. Holland , Thomas West , James M. Guyer , Richard W. Coyle , Michael L. Ziegler , Michael B. Druke
发明人： Edward Rasala , Steven Wallach , Carl J. Alsing , Kenneth D. Holberger , Charles J. Holland , Thomas West , James M. Guyer , Richard W. Coyle , Michael L. Ziegler , Michael B. Druke
IPC分类号： G06F9/22 , G06F9/26 , G06F9/30 , G06F9/34 , G06F11/10 , G06F11/14 , G06F12/08 , G06F12/10 , G06F12/14 , G06F13/00 , G06F9/36
CPC分类号： G06F12/0857 , G06F11/10 , G06F11/14 , G06F12/0802 , G06F12/1009 , G06F12/14 , G06F9/26 , G06F9/3013 , G06F9/30185 , G06F9/30196 , G06F9/342 , G06F11/106
摘要： A data processing system which handles thirty-two bit logical addresses which can be derived from either sixteen bit logical addresses or thirty-two bit logical addresses, the latter being translated into physical addresses by unique translation means. The system includes means for decoding macro-instructions of both a basic and an extended instruction set, each macro-instruction containing in itself selected bit patterns which uniquely identify which type of instruction is to be decoded. The decoded macro-instructions provide the starting address of one or more micro-instructions, which address is supplied to a unique micro-instruction sequencing unit which appropriately decodes a selected field of each micro-instruction to obtain each successive micro-instruction. The system uses hierarchical memory storage using eight storage segments (rings), access to the rings being controlled in a privileged manner according to different levels of privilege. The memory system uses a bank of main memory modules which interface with the central processor system via a dual port cache memory, block data transfers between the main memory and the cache memory being controlled by a bank controller unit.
摘要翻译： 一种数据处理系统，其处理可从十六位逻辑地址或三十二位逻辑地址导出的二十二位逻辑地址，后者通过唯一的转换装置转换成物理地址。 该系统包括用于解码基本指令集和扩展指令集的宏指令的装置，每个宏指令本身都包含唯一地标识要被解码的指令类型的所选位模式。 解码的宏指令提供一个或多个微指令的起始地址，该地址被提供给唯一的微指令排序单元，其适当地解码每个微指令的选定字段以获得每个连续的微指令。 该系统使用八个存储段（环）的分层存储器存储，根据不同级别的权限访问以特权方式控制的环。 存储器系统使用一组主存储器模块，其通过双端口高速缓冲存储器与中央处理器系统连接，在主存储器和高速缓冲存储器之间块数据传输由存储体控制器单元控制。
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公开(公告)号：US08539113B2
公开(公告)日：2013-09-17
申请号：US13161894
申请日：2011-06-16
申请人： Michael L. Ziegler
发明人： Michael L. Ziegler
摘要： Techniques described herein provide for sending and receiving messages. The messages are associated with streams. Indicators associated with the streams determine if the messages are sent.
摘要翻译： 本文描述的技术提供了发送和接收消息。 消息与流相关联。 与流相关联的指示符确定消息是否被发送。
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