公开(公告)号：US20090158285A1

公开(公告)日：2009-06-18

申请号：US12239508

申请日：2008-09-26

Applicant: Mi Young Lee ,  Han Jin Cho

Inventor： Mi Young Lee ,  Han Jin Cho

IPC: G06F9/46

CPC classification number: G06F9/5011 ,  G06F2209/5014

Abstract: An apparatus for controlling a resource sharing schedule in a multi-decoding system including a multi-decoder formed of a plurality of resources, the apparatus including: a storage unit storing status information of the resources and information required in controlling the resource sharing schedule; and a controller, when a source resource requests assignment of a target resource, assigning the target resource, outputting information of the target resource to the source resource, and updating statuses of the resources, wherein the apparatus controls the resource sharing schedule while bidirectionally connected to the resources to share the resources between the multi-decoders. Accordingly, it is possible to reduce an overall decoding time and controlling a resource usage schedule.

Abstract translation: 一种用于在包括由多个资源构成的多解码器的多解码系统中控制资源共享调度的装置，所述装置包括：存储单元，存储资源的状态信息和控制资源共享进度所需的信息; 以及控制器，当源资源请求分配目标资源时，分配所述目标资源，将所述目标资源的信息输出到所述源资源，以及更新所述资源的状态，其中，所述装置控制所述资源共享进度，同时双向地连接到 资源共享多解码器之间的资源。 因此，可以减少整体解码时间并控制资源使用进度。

公开(公告)号：US06819708B1

公开(公告)日：2004-11-16

申请号：US09716185

申请日：2000-11-17

Applicant: In Gi Lim ,  Suk Ho Lee ,  Kyung Soo Kim ,  Han Jin Cho

Inventor： In Gi Lim ,  Suk Ho Lee ,  Kyung Soo Kim ,  Han Jin Cho

IPC: H04B169

CPC classification number: H04L27/2071

Abstract: A modulator for an IMT-2000 synchronous mobile station in a digital telecommunication and modulating method thereof, and more particularly, an OCQPSK modulator using FIR filters, each for performing 1:4 interpolation operations for 4 input data and a modulating method thereof. The orthogonal complex quadrature phase shift keying OCQPSK modulating apparatus uses a 1-bit input FIR filter that includes pseudo noise spreading for bifurcating 1-bit data inputted from input channels and pseudo-spreading the bifurcated 1-bit data, an FIR filter for receiving the 1-bit data and performing a filtering operation for pulse shaping, a gain multiplying block for multiplying filtered data outputted from the FIR filter by a gain for respective channels, and a channel adder block for adding data outputted from the gain multiplying block to output I channel and Q channel signals.

Abstract translation: 一种用于数字电信中的IMT-2000同步移动台的调制器及其调制方法，更具体地，涉及使用FIR滤波器的OCQPSK调制器，每个用于对4个输入数据进行1：4插值运算及其调制方法。 正交复数正交相移键控OCQPSK调制装置使用包括伪噪声扩展的1比特输入FIR滤波器，用于对从输入通道输入的1比特数据进行分叉，并对分叉的1比特数据进行伪扩展; FIR滤波器，用于接收 1位数据并执行用于脉冲整形的滤波操作，用于将从FIR滤波器输出的滤波数据乘以各通道的增益的增益乘法块和用于将从增益乘法块输出的数据加到输出I的通道加法器块 通道和Q通道信号。

公开(公告)号：US08539325B2

公开(公告)日：2013-09-17

申请号：US12972289

申请日：2010-12-17

Applicant: In San Jeon ,  Hyuk Kim ,  Han Jin Cho

Inventor： In San Jeon ,  Hyuk Kim ,  Han Jin Cho

IPC: G06F11/00

CPC classification number: H03M13/6525 ,  H03M13/2957 ,  H03M13/3922 ,  H03M13/3927

Abstract: An apparatus for generating a parity bit for turbo decoding, and a MAP (Maximum A Posteriori) apparatus are provided. The apparatus for generating a parity bit for turbo decoding includes: a index converter calculating forward and reverse state matrices with respect to a parity bit by maintaining or changing the relationship between the forward and reverse state matrices with respect to information bits and input symbols according to an encoder state; and a parity calculation unit calculating a parity bit by using the forward and reverse state matrices calculated by the parity state matric calculation unit.

Abstract translation: 提供了一种用于生成用于turbo解码的奇偶校验位的装置，以及MAP（Maximum A Reareriori）装置。 用于生成用于turbo解码的奇偶校验位的装置包括：索引转换器，相对于奇偶校验位，通过根据信息比特和输入符号保持或改变正向和反向状态矩阵之间的关系来计算正向和反向状态矩阵 编码器状态; 以及奇偶校验计算单元，通过使用由奇偶校验状态矩阵计算单元计算的正向和反向状态矩阵来计算奇偶校验位。

公开(公告)号：US07464275B2

公开(公告)日：2008-12-09

申请号：US11213059

申请日：2005-08-26

Applicant: Tae Young Lim ,  Han Jin Cho ,  Soon Il Yeo ,  Ig Kyun Kim ,  Kyoung Seon Shin ,  Hee Bum Jung

Inventor： Tae Young Lim ,  Han Jin Cho ,  Soon Il Yeo ,  Ig Kyun Kim ,  Kyoung Seon Shin ,  Hee Bum Jung

IPC: G06F1/26

CPC classification number: G06F1/26

Abstract: Provided is an apparatus for controlling multiple powers which is capable of turning on and off the multiple powers in their priorities for systems or components to be supplied with the multiple powers such as a liquid crystal display (LCD) module. In the apparatus for controlling multiple powers, an on-signal of high level is applied to an input terminal, and an output of a control signal generating unit is sequentially changed to a high level whenever a clock is applied to a clock signal input terminal by one period, so that outputs of the multiple powers are sequentially output. In addition, an off signal of low level is applied to the input terminal, and an output of the control signal generating unit is changed to a low level in a reversal order whenever a clock is applied to the clock signal input terminal by one period, so that outputs of the multiple powers are interrupted in the reversal order.

Abstract translation: 本发明提供了一种用于控制多个功率的装置，其能够在要提供给诸如液晶显示器（LCD）模块的多个功率的系统或组件的优先级中打开和关闭多个功率。 在用于控制多个功率的装置中，将高电平的接通信号施加到输入端，并且每当时钟被施加到时钟信号输入端时，控制信号产生单元的输出被顺序地改变为高电平 一个周期，从而顺序输出多个功率的输出。 此外，只要将时钟施加到时钟信号输入端子一个周期，则将低电平的关闭信号施加到输入端子，并且控制信号产生单元的输出以反转次序改变为低电平， 使得多个功率的输出以反转顺序中断。

公开(公告)号：US20070162645A1

公开(公告)日：2007-07-12

申请号：US11524069

申请日：2006-09-20

Applicant: Jin Ho Han ,  Han Jin Cho

Inventor： Jin Ho Han ,  Han Jin Cho

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Provided is a communication system for improving utilization of on-chip communication architecture and eliminating waiting of a master to use a bus. The communication system includes: a direct memory access controller handling high-capacity data communication among a memory and peripheral devices; a communication switch connected with the direct memory access controller, transferring a header storing information on a location of a passive circuit and a continuous transfer size, and an initial address from an active circuit to the passive circuit, and sending and receiving data to/from the direct memory access controller; and a memory controller sending and receiving the data and the address to/from the direct memory access controller. According to the communication system, a request of an active circuit is not delayed between on-chip circuits, several active circuits can simultaneously transfer data, data communication rate between passive circuits increases, and communication congestion between the passive circuits can be controlled.

Abstract translation: 提供了一种用于提高片上通信体系结构的利用并消除主机等待使用总线的通信系统。 通信系统包括：直接存储器访问控制器，用于处理存储器和外围设备之间的高容量数据通信; 与直接存储器存取控制器连接的通信开关，将存储有关无源电路的位置的信息和连续的传送大小的报头以及从有源电路的初始地址传送到无源电路，以及发送和接收数据到/从 直接存储器存取控制器; 以及存储器控制器向/从直接存储器存取控制器发送和接收数据和地址。 根据通信系统，有源电路的请求在片上电路之间不被延迟，几个有源电路可以同时传输数据，无源电路之间的数据通信速率增加，并且可以控制无源电路之间的通信拥塞。

公开(公告)号：US06584212B1

公开(公告)日：2003-06-24

申请号：US09475224

申请日：1999-12-30

Applicant: Seong Mo Park ,  Jin Jong Cha ,  Han Jin Cho

Inventor： Seong Mo Park ,  Jin Jong Cha ,  Han Jin Cho

IPC: G06K900

CPC classification number: H04N19/533 ,  G06T7/238 ,  G06T2200/28 ,  H04N19/43

Abstract: An apparatus for motion estimation with control part implemented by state transition diagram without adding delay circuits to processing elements, and capable of maintaining a regular data flow and easily implementing hardware to improve a power consume and speed is disclosed. The apparatus comprises a first and second storage parts for storing data; a measurement part for finding an absolute difference between the data; a step decision part for determining a minimum value; and a control part implemented by state transition diagram.

Abstract translation: 公开了一种用于通过状态转移图实现的具有控制部分的运动估计的装置，而不向处理元件添加延迟电路，并且能够保持规则的数据流并且容易地实现硬件以提高功耗和速度。 该装置包括用于存储数据的第一和第二存储部件; 用于求出数据之间的绝对差的测量部分; 用于确定最小值的步骤确定部分; 以及通过状态转换图实现的控制部分。

公开(公告)号：US06400932B1

公开(公告)日：2002-06-04

申请号：US09454389

申请日：1999-12-03

Applicant: Chang Jun Oh ,  Jong Kee Kwon ,  Jong Ryul Lee ,  Won Chul Song ,  Hee Bum Jung ,  Kyung Soo Kim ,  Han Jin Cho ,  Ook Kim

Inventor： Chang Jun Oh ,  Jong Kee Kwon ,  Jong Ryul Lee ,  Won Chul Song ,  Hee Bum Jung ,  Kyung Soo Kim ,  Han Jin Cho ,  Ook Kim

IPC: H04B118

CPC classification number: H03H11/0422 ,  H03L7/06

Abstract: The present invention relates to a tuning circuit, more specifically to a tuning circuit for continuous-time filter capable of making exact the Gm value to minimize the variation of the cutoff frequency due to the variation of process in the Gm-C type of continuous-time filter. According to the invention, a frequency tuning circuit is provided which comprises integrating means for generating a signal discharging from a first reference voltage to a first predetermined value and a signal charging from a second reference voltage to a second predetermined value; offset sampling means for sampling the offset voltages of the Gm cells by receiving a current multiplied by the offset voltages from the Gm cells included in the integrating means and providing a feedback path between the output nodes and the input nodes of the included Gm cells; comparative signal generating means for generating a comparative signal by generating a reference signal by dividing a clock inputted from the external, receiving the signal discharging from the first reference voltage to the first predetermined value and the signal charging from the second reference voltage to the second predetermined value from the integrating means, and comparing the actual intersection and the target intersection of these signals; and control means for generating a control signal to regulate the Gm values of the integrating means and the offset sampling means by receiving the reference signal and the comparative signal from the comparative signal generating means and detecting the phase differences therebetween.

Abstract translation: 调谐电路技术领域本发明涉及一种调谐电路，更具体地说涉及一种用于连续时间滤波器的调谐电路，其能够精确地确定Gm值，以使由于Gm-C型连续时间滤波器中的工艺变化引起的截止频率的变化最小化， 时间过滤器。 根据本发明，提供了一种频率调谐电路，其包括用于产生从第一参考电压放电到第一预定值的信号的积分装置和从第二参考电压到第二预定值的信号充电; 偏移采样装置，用于通过接收与积分装置中包括的Gm单元的偏移电压相乘的电流来对Gm单元的偏移电压进行采样，并在输出节点和所包括的Gm单元的输入节点之间提供反馈路径; 比较信号发生装置，用于通过将从外部输入的时钟分频，将从第一参考电压放电的信号接收到第一预定值和从第二参考电压到第二预定值的信号充电来产生参考信号， 从积分装置获取值，并比较这些信号的实际交点和目标交点; 以及控制装置，用于通过从比较信号发生装置接收参考信号和比较信号并检测它们之间的相位差，产生控制信号以调节积分装置和偏移采样装置的Gm值。

公开(公告)号：US06201487B1

公开(公告)日：2001-03-13

申请号：US09368347

申请日：1999-08-05

Applicant: Seong Mo Park ,  Jin Jong Cha ,  Han Jin Cho

Inventor： Seong Mo Park ,  Jin Jong Cha ,  Han Jin Cho

IPC: H03M740

CPC classification number: H03M7/46

Abstract: An error detection circuit for detecting errors occurring in a data obtained by decoding a compressed image data block by block in a line length decoding system, includes a first storage device for temporarily storing the run representing the number of zeros (‘0’s) in the compressed image data and an EOB signal externally inputted, a selection signal generator for generating a first and a second selection signal in response to the EOB signal supplied from the first storage device, a first selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the first selection signal, a second selection circuit for selectively transferring the run supplied by the first storage device or ground signal according to the second selection signal, a reference value generator for generating a reference value based on the output signal of the first selection circuit according to an operation control signal externally inputted, accumulator for accumulating the output of the second selection circuit based on the feedback signal from a second storage device, the second storage device temporarily storing the output of the accumulator, and an error detector for detecting the errors based on the reference value and the output of the second storage device.

Abstract translation: 一种误差检测电路，用于检测通过在行长解码系统中逐块解码压缩图像数据而获得的数据中发生的错误，包括：第一存储装置，用于临时存储表示压缩的零数量（“0”）的运行 图像数据和外部输入的EOB信号，响应于从第一存储装置提供的EOB信号产生第一和第二选择信号的选择信号发生器，用于选择性地传送由第一存储装置提供的运行的第一选择电路 或接地信号，第二选择电路，用于根据第二选择信号选择性地传送由第一存储装置提供的运行或接地信号;参考值发生器，用于基于第一选择信号的输出信号产生参考值; 第一选择电路根据外部输入的操作控制信号，蓄电池 基于来自第二存储装置的反馈信号累积第二选择电路的输出，第二存储装置临时存储累加器的输出，以及错误检测器，用于基于参考值和第二选择电路的输出检测错误 储存设备。