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    ANISOTROPIC DIFFUSION METHOD AND APPARATUS BASED ON DIRECTION OF EDGE
    3.
    发明申请
    ANISOTROPIC DIFFUSION METHOD AND APPARATUS BASED ON DIRECTION OF EDGE 审中-公开
    基于边缘方向的各向异性扩散方法和装置

    公开(公告)号：US20100111438A1

    公开(公告)日：2010-05-06

    申请号：US12612055

    申请日：2009-11-04

    Applicant: June Young Chang ,  Han Jin Cho ,  Young Hwan Bae ,  Won Jong Kim ,  Mi Young Lee ,  Ju Yeob Kim ,  Guee Sang Lee ,  In San Jeon

    Inventor： June Young Chang ,  Han Jin Cho ,  Young Hwan Bae ,  Won Jong Kim ,  Mi Young Lee ,  Ju Yeob Kim ,  Guee Sang Lee ,  In San Jeon

    IPC: G06K9/40

    CPC classification number: G06T5/002 ,  G06T5/20 ,  G06T2207/20012 ,  G06T2207/20192

    Abstract: An anisotropic diffusion method and apparatus based on the direction of an edge are disclosed. In the anisotropic diffusion apparatus, directional pattern masking is performed to determine the direction of an edge in an image including noise, and values obtained through the directional pattern masking are convoluted to calculate the magnitude of an image. If the calculated magnitude value of the edge is larger than a threshold value, the edge of the image is preserved, while if the calculated magnitude value of the edge is not larger than the threshold value, noise cancellation is strengthened, whereby noise can be effectively canceled (or concealed) while preserving the edge representing the characteristics of the image, and thus, an image of high quality can be obtained.

    Abstract translation: 公开了一种基于边缘方向的各向异性扩散方法和装置。 在各向异性扩散装置中，执行方向图案掩蔽以确定包括噪声的图像中的边缘的方向，并且通过方向图案掩模获得的值被卷积以计算图像的大小。 如果边缘的计算幅度值大于阈值，则图像的边缘被保留，而如果所计算的边缘的幅度值不大于阈值，则噪声消除被加强，从而可以有效地产生噪声 取消（或隐藏），同时保留表示图像特征的边缘，从而可以获得高质量的图像。

    APPARATUS AND METHOD FOR CONTROLLING RESOURCE SHARING SCHEDULE IN MULTI-DECODING SYSTEM
    5.
    发明申请
    APPARATUS AND METHOD FOR CONTROLLING RESOURCE SHARING SCHEDULE IN MULTI-DECODING SYSTEM 审中-公开
    用于控制多解码系统中的资源共享时间表的装置和方法

    公开(公告)号：US20090158285A1

    公开(公告)日：2009-06-18

    申请号：US12239508

    申请日：2008-09-26

    Applicant: Mi Young Lee ,  Han Jin Cho

    Inventor： Mi Young Lee ,  Han Jin Cho

    IPC: G06F9/46

    CPC classification number: G06F9/5011 ,  G06F2209/5014

    Abstract: An apparatus for controlling a resource sharing schedule in a multi-decoding system including a multi-decoder formed of a plurality of resources, the apparatus including: a storage unit storing status information of the resources and information required in controlling the resource sharing schedule; and a controller, when a source resource requests assignment of a target resource, assigning the target resource, outputting information of the target resource to the source resource, and updating statuses of the resources, wherein the apparatus controls the resource sharing schedule while bidirectionally connected to the resources to share the resources between the multi-decoders. Accordingly, it is possible to reduce an overall decoding time and controlling a resource usage schedule.

    Abstract translation: 一种用于在包括由多个资源构成的多解码器的多解码系统中控制资源共享调度的装置，所述装置包括：存储单元，存储资源的状态信息和控制资源共享进度所需的信息; 以及控制器，当源资源请求分配目标资源时，分配所述目标资源，将所述目标资源的信息输出到所述源资源，以及更新所述资源的状态，其中，所述装置控制所述资源共享进度，同时双向地连接到 资源共享多解码器之间的资源。 因此，可以减少整体解码时间并控制资源使用进度。

    Delay circuit for low power ring oscillator
    6.
    发明授权
    Delay circuit for low power ring oscillator 失效
    低功耗环形振荡器的延迟电路

    公开(公告)号：US08188801B2

    公开(公告)日：2012-05-29

    申请号：US12878476

    申请日：2010-09-09

    Applicant: Myeung Su Kim ,  Han Jin Cho ,  Joon Hyung Lim ,  Kyung Hee Hong ,  Yong Il Kwon

    Inventor： Myeung Su Kim ,  Han Jin Cho ,  Joon Hyung Lim ,  Kyung Hee Hong ,  Yong Il Kwon

    IPC: H03K3/03

    CPC classification number: H03K3/0322 ,  H03K3/012

    Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

    Abstract translation: 这里公开了一种用于低功率环形振荡器的延迟电路。 延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

    WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION
    7.
    发明申请
    WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION 有权
    具有自我感应功能的无线通信设备

    公开(公告)号：US20100150041A1

    公开(公告)日：2010-06-17

    申请号：US12430313

    申请日：2009-04-27

    Applicant: Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

    Inventor： Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

    IPC: G08C17/00

    CPC classification number: H04Q9/02 ,  H04Q2209/43 ,  H04Q2209/883

    Abstract: Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.

    Abstract translation: 公开了一种具有自感功能的无线通信装置，其可以通过使用唤醒功能而不使用单独的传感器来检测对象。 该无线通信装置包括与形成无线网络的服务器无线通信的通信单元，以及当通信单元处于睡眠模式时，在服务器的控制下唤醒通信单元的唤醒单元，并且感测到 根据反射信号在预设通信范围内对象，该反射信号是从通信单元发送之后由对象反射的信号。

    Crossbar switch architecture for multi-processor SoC platform
    8.
    发明授权
    Crossbar switch architecture for multi-processor SoC platform 有权
    交叉开关架构为多处理器SoC平台

    公开(公告)号：US07554355B2

    公开(公告)日：2009-06-30

    申请号：US11607515

    申请日：2006-12-01

    Applicant: June Young Chang ,  Han Jin Cho

    Inventor： June Young Chang ,  Han Jin Cho

    IPC: H04L12/50 ,  H03K17/00

    CPC classification number: H04L49/101 ,  H04L49/15 ,  H04L49/45

    Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

    Abstract translation: 提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易 增加并具有简单的控制结构。 交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与 每行最后一列的多路复用器与该行的输入/输出线连接。

    Crossbar switch architecture for multi-processor SoC platform
    10.
    发明申请
    Crossbar switch architecture for multi-processor SoC platform 有权
    交叉开关架构为多处理器SoC平台

    公开(公告)号：US20070126474A1

    公开(公告)日：2007-06-07

    申请号：US11607515

    申请日：2006-12-01

    Applicant: June Young Chang ,  Han Jin Cho

    Inventor： June Young Chang ,  Han Jin Cho

    IPC: H03K19/173

    CPC classification number: H04L49/101 ,  H04L49/15 ,  H04L49/45

    Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

    Abstract translation: 提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易 增加并具有简单的控制结构。 交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与 每行最后一列的多路复用器与该行的输入/输出线连接。

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