中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

28 records (took 0.019 seconds)

    On-chip network interfacing apparatus and method
    1.
    发明授权
    On-chip network interfacing apparatus and method 有权
    片上网络接口设备及方法

    公开(公告)号：US07711787B2

    公开(公告)日：2010-05-04

    申请号：US11300731

    申请日：2005-12-14

    Applicant: Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

    Inventor： Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

    IPC: G06F15/16

    CPC classification number: H04L49/10 ,  H04L49/109 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/503

    Abstract: An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.

    Abstract translation: 提供了片上网络接口设备和方法。 该装置包括多个片上网络端口; 从所述片上网络端口的第一片上网络端口接收数据并将所接收的数据发送到所述片上网络端口的第二片上网络端口; 以及接口单元，其连接从根据AMBA片上总线协议设计的模块接收的高级单片机总线架构（AMBA）信号，并将所述接口结果输出到所述第一片上网络端口; 并且连接从第一片上网络端口接收的片上网络信号，并将接口结果输出到模块。 因此，可以通过将根据AMBA 2.0片上总线协议的信号与根据片上网络协议的信号进行接口来以增加的速度建立通信。

    Communication system for data transfer between on-chip circuits
    2.
    发明申请
    Communication system for data transfer between on-chip circuits 审中-公开
    用于片上电路之间数据传输的通信系统

    公开(公告)号：US20070162645A1

    公开(公告)日：2007-07-12

    申请号：US11524069

    申请日：2006-09-20

    Applicant: Jin Ho Han ,  Han Jin Cho

    Inventor： Jin Ho Han ,  Han Jin Cho

    IPC: G06F13/28

    CPC classification number: G06F13/28

    Abstract: Provided is a communication system for improving utilization of on-chip communication architecture and eliminating waiting of a master to use a bus. The communication system includes: a direct memory access controller handling high-capacity data communication among a memory and peripheral devices; a communication switch connected with the direct memory access controller, transferring a header storing information on a location of a passive circuit and a continuous transfer size, and an initial address from an active circuit to the passive circuit, and sending and receiving data to/from the direct memory access controller; and a memory controller sending and receiving the data and the address to/from the direct memory access controller. According to the communication system, a request of an active circuit is not delayed between on-chip circuits, several active circuits can simultaneously transfer data, data communication rate between passive circuits increases, and communication congestion between the passive circuits can be controlled.

    Abstract translation: 提供了一种用于提高片上通信体系结构的利用并消除主机等待使用总线的通信系统。 通信系统包括：直接存储器访问控制器，用于处理存储器和外围设备之间的高容量数据通信; 与直接存储器存取控制器连接的通信开关，将存储有关无源电路的位置的信息和连续的传送大小的报头以及从有源电路的初始地址传送到无源电路，以及发送和接收数据到/从 直接存储器存取控制器; 以及存储器控制器向/从直接存储器存取控制器发送和接收数据和地址。 根据通信系统，有源电路的请求在片上电路之间不被延迟，几个有源电路可以同时传输数据，无源电路之间的数据通信速率增加，并且可以控制无源电路之间的通信拥塞。

    Delay circuit for low power ring oscillator
    3.
    发明授权
    Delay circuit for low power ring oscillator 失效
    低功耗环形振荡器的延迟电路

    公开(公告)号：US08188801B2

    公开(公告)日：2012-05-29

    申请号：US12878476

    申请日：2010-09-09

    Applicant: Myeung Su Kim ,  Han Jin Cho ,  Joon Hyung Lim ,  Kyung Hee Hong ,  Yong Il Kwon

    Inventor： Myeung Su Kim ,  Han Jin Cho ,  Joon Hyung Lim ,  Kyung Hee Hong ,  Yong Il Kwon

    IPC: H03K3/03

    CPC classification number: H03K3/0322 ,  H03K3/012

    Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1−; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2−; a differential output terminal that outputs differential output signals Vout+ and Vout− generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

    Abstract translation: 这里公开了一种用于低功率环形振荡器的延迟电路。 延迟电路包括：一对N型晶体管，其接收第一差分输入信号Vin1 +和Vin1-; 一对P型晶体管，接收第二差分输入信号Vin2 +和Vin2-; 差分输出端子，其输出从所述一对N型晶体管和所述一对P型晶体管产生的差分输出信号Vout +和Vout-; N型检测器，其向所述一对N型晶体管提供体电压; 以及向该P型晶体管对提供体电压的P型检测器。

    WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION
    5.
    发明申请
    WIRELESS COMMUNICATION APPARATUS HAVING SELF SENSING FUNCTION 有权
    具有自我感应功能的无线通信设备

    公开(公告)号：US20100150041A1

    公开(公告)日：2010-06-17

    申请号：US12430313

    申请日：2009-04-27

    Applicant: Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

    Inventor： Joon Hyung LIM ,  Tah Joon Park ,  Han Jin Cho ,  Myeung Su Kim ,  Sang Hoon Hwang ,  Kyung Hee Hong ,  Yong Il Kwon

    IPC: G08C17/00

    CPC classification number: H04Q9/02 ,  H04Q2209/43 ,  H04Q2209/883

    Abstract: Disclosed is a wireless communication apparatus having a self sensing function, which can detect an object by use of a wake-up function without employing a separate sensor. The wireless communication apparatus includes a communication unit wirelessly communicating with a server forming a wireless network, and a wake-up unit waking up the communication unit under the control of the server when the communication unit is in sleep mode, and sensing the presence of an object within a preset communication range according to a reflection signal, which is a signal reflected by the object after being transmitted from the communication unit.

    Abstract translation: 公开了一种具有自感功能的无线通信装置，其可以通过使用唤醒功能而不使用单独的传感器来检测对象。 该无线通信装置包括与形成无线网络的服务器无线通信的通信单元，以及当通信单元处于睡眠模式时，在服务器的控制下唤醒通信单元的唤醒单元，并且感测到 根据反射信号在预设通信范围内对象，该反射信号是从通信单元发送之后由对象反射的信号。

    Crossbar switch architecture for multi-processor SoC platform
    6.
    发明授权
    Crossbar switch architecture for multi-processor SoC platform 有权
    交叉开关架构为多处理器SoC平台

    公开(公告)号：US07554355B2

    公开(公告)日：2009-06-30

    申请号：US11607515

    申请日：2006-12-01

    Applicant: June Young Chang ,  Han Jin Cho

    Inventor： June Young Chang ,  Han Jin Cho

    IPC: H04L12/50 ,  H03K17/00

    CPC classification number: H04L49/101 ,  H04L49/15 ,  H04L49/45

    Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

    Abstract translation: 提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易 增加并具有简单的控制结构。 交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与 每行最后一列的多路复用器与该行的输入/输出线连接。

    Crossbar switch architecture for multi-processor SoC platform
    9.
    发明申请
    Crossbar switch architecture for multi-processor SoC platform 有权
    交叉开关架构为多处理器SoC平台

    公开(公告)号：US20070126474A1

    公开(公告)日：2007-06-07

    申请号：US11607515

    申请日：2006-12-01

    Applicant: June Young Chang ,  Han Jin Cho

    Inventor： June Young Chang ,  Han Jin Cho

    IPC: H03K19/173

    CPC classification number: H04L49/101 ,  H04L49/15 ,  H04L49/45

    Abstract: Provided is a crossbar switch architecture appropriate to a multi-processor system-on-a-chip (SoC) platform including a plurality of masters and slaves, capable of high-speed data transfer, allowing the number of masters or slaves therein to be easily increased, and having a simple control structure. The crossbar switch architecture includes 2×1 multiplexers connected in a matrix form consisting of rows and columns. The 2×1 multiplexers each have one input line connected with an output line of a multiplexer at a front column of the same row, and the other input line connected with an input/output line of a column including the corresponding multiplexer, and an output line of a multiplexer at the last column of each row is connected with an input/output line of the row.

    Abstract translation: 提供了一种适用于多处理器片上系统（SoC）平台的交叉开关架构，其包括能够进行高速数据传输的多个主机和从机，从而允许其中的主机或从机的数量容易 增加并具有简单的控制结构。 交叉开关架构包括以行和列组成的矩阵形式连接的2x1多路复用器。 2×1复用器各自具有一个输入线，与同一行前列的多路复用器的输出线连接，另一条输入线与包括相应多路复用器的列的输入/输出线连接，另一条输入线与 每行最后一列的多路复用器与该行的输入/输出线连接。

Patent Agency Ranking