公开(公告)号：US20070162645A1

公开(公告)日：2007-07-12

申请号：US11524069

申请日：2006-09-20

Applicant: Jin Ho Han ,  Han Jin Cho

Inventor： Jin Ho Han ,  Han Jin Cho

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Provided is a communication system for improving utilization of on-chip communication architecture and eliminating waiting of a master to use a bus. The communication system includes: a direct memory access controller handling high-capacity data communication among a memory and peripheral devices; a communication switch connected with the direct memory access controller, transferring a header storing information on a location of a passive circuit and a continuous transfer size, and an initial address from an active circuit to the passive circuit, and sending and receiving data to/from the direct memory access controller; and a memory controller sending and receiving the data and the address to/from the direct memory access controller. According to the communication system, a request of an active circuit is not delayed between on-chip circuits, several active circuits can simultaneously transfer data, data communication rate between passive circuits increases, and communication congestion between the passive circuits can be controlled.

Abstract translation: 提供了一种用于提高片上通信体系结构的利用并消除主机等待使用总线的通信系统。 通信系统包括：直接存储器访问控制器，用于处理存储器和外围设备之间的高容量数据通信; 与直接存储器存取控制器连接的通信开关，将存储有关无源电路的位置的信息和连续的传送大小的报头以及从有源电路的初始地址传送到无源电路，以及发送和接收数据到/从 直接存储器存取控制器; 以及存储器控制器向/从直接存储器存取控制器发送和接收数据和地址。 根据通信系统，有源电路的请求在片上电路之间不被延迟，几个有源电路可以同时传输数据，无源电路之间的数据通信速率增加，并且可以控制无源电路之间的通信拥塞。

公开(公告)号：US07711787B2

公开(公告)日：2010-05-04

申请号：US11300731

申请日：2005-12-14

Applicant: Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

Inventor： Jin Ho Han ,  Young Hwan Bae ,  Han Jin Cho ,  Jun Young Chang

IPC: G06F15/16

CPC classification number: H04L49/10 ,  H04L49/109 ,  H04L49/3009 ,  H04L49/3018 ,  H04L49/503

Abstract: An on-chip network interfacing apparatus and method are provided. The apparatus includes a plurality of on-chip network ports; a switch receiving data from a first on-chip network port of the on-chip network ports and transmitting the received data to a second on-chip network port of the on-chip network ports; and an interface unit interfacing an advanced microcontroller bus architecture (AMBA) signal received from an module, which is designed according to an AMBA on-chip bus protocol, and outputting the interfacing result to the first on-chip network port; and interfacing the on-chip network signal received from the first on-chip network port, and outputting the interfacing result to the module. Accordingly, it is possible to establish communications at increased speeds by interfacing a signal according to the AMBA 2.0 on-chip bus protocol with a signal according to the on-chip network protocol.

Abstract translation: 提供了片上网络接口设备和方法。 该装置包括多个片上网络端口; 从所述片上网络端口的第一片上网络端口接收数据并将所接收的数据发送到所述片上网络端口的第二片上网络端口; 以及接口单元，其连接从根据AMBA片上总线协议设计的模块接收的高级单片机总线架构（AMBA）信号，并将所述接口结果输出到所述第一片上网络端口; 并且连接从第一片上网络端口接收的片上网络信号，并将接口结果输出到模块。 因此，可以通过将根据AMBA 2.0片上总线协议的信号与根据片上网络协议的信号进行接口来以增加的速度建立通信。

公开(公告)号：US08904199B2

公开(公告)日：2014-12-02

申请号：US13207484

申请日：2011-08-11

Applicant: Jin Ho Han

Inventor： Jin Ho Han

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26

CPC classification number: G06F1/324 ,  G06F1/26 ,  Y02D10/126

Abstract: The present invention relates to an apparatus for controlling power of mufti core processor, which includes a power control device by core unit, controls a plurality of power-related parameters by core unit, and thus decreases a load for power management and enables realization of a low power multi core processor through minute power control. The apparatus includes a processor core adapted to provide code information on an application program for executing to a power regulation controller, and a power regulation controller adapted to receive the code information on the application program from the processor core to determine an operation frequency of the processor core, set an operation voltage, a clock-gating value and a power-gating value according to the determined operation frequency, and provide the set values and voltage to the processor core.

Abstract translation: 本发明涉及一种用于控制核心处理器的功率的装置，其包括核心单元的功率控制装置，通过核心单元控制多个与功率有关的参数，从而减少用于电力管理的负载，并且能够实现 低功耗多核处理器，通过微功率控制。 所述设备包括处理器核心，其适于提供关于用于执行功率调节控制器的应用程序的代码信息;以及功率调节控制器，其适于从所述处理器核心接收关于所述应用程序的代码信息，以确定所述处理器的操作频率 根据所确定的工作频率设置工作电压，时钟门控值和电源门控值，并将设定值和电压提供给处理器核心。

公开(公告)号：US20110064137A1

公开(公告)日：2011-03-17

申请号：US12861118

申请日：2010-08-23

Applicant: Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/50 ,  H04N7/26

CPC classification number: H04N19/53 ,  H04N19/194 ,  H04N19/43 ,  H04N19/433 ,  H04N19/61

Abstract: There is provided a video encoding apparatus allowing for enhanced video encoding speed according to the H.264 video coding standard. The video encoding apparatus allows the memories included in the video encoding apparatus to be shared by a plurality of elements through the rearrangement and the structural change of the memories considering an efficient hierarchical motion estimation algorithm. Therefore, the video encoding apparatus has the effects of reducing the amount of transmitted and received data between the frame memory and the video encoding apparatus and enhancing video encoding speed.

Abstract translation: 提供了根据H.264视频编码标准允许增强的视频编码速度的视频编码装置。 视频编码装置允许考虑到有效的分级运动估计算法，通过重排和存储器的结构变化，包括在视频编码装置中的存储器被多个元件共享。 因此，视频编码装置具有减少帧存储器和视频编码装置之间的发送和接收数据量并提高视频编码速度的效果。

公开(公告)号：US08196471B2

公开(公告)日：2012-06-12

申请号：US11909293

申请日：2006-03-24

Applicant: Jin Ho Han ,  Dong Hyun Kim ,  In Seong Song

Inventor： Jin Ho Han ,  Dong Hyun Kim ,  In Seong Song

IPC: G01N29/00 ,  A61B8/14

CPC classification number: A61B8/12 ,  A61B8/4461

Abstract: The present invention relates to an ultrasonic probe for producing a real-time three dimensional live action image (a four dimensional image), which has a long lifetime, and an improved image quality, can prevent malfunction. The ultrasonic probe for producing a four dimensional image includes power transmission means for transmission of power from an upright motor to a module (2) having acoustic elements for swinging the module, the power transmission means includes a first link (20) having a horizontal portion (22) directly connected to a motor shaft, and a sloped portion projected upward from one side end of the horizontal portion at an angle in conformity with a locus of a swing action of the module, and a second link (21) comprising a horizontal (29) having an interlocking connected thereto and a pair of parallel portion (30) and (31) projected upwardly from opposite ends of the horizontal portion, such that the second link is interlocked along the first link in a state of being interposed between the first link and the module, wherein the interlocking shaft (28) is connected with an inclined portion of the first link by a shaft and the pair of parallel portions is mounting to a lower side of the module in a horizontal direction with a shaft.

Abstract translation: 本发明涉及一种用于制造具有长寿命和改进的图像质量的实时三维实况动作图像（四维图像）的超声波探头，可以防止故障。 用于产生四维图像的超声波探头包括用于将功率从直立马达传输到具有用于摆动模块的声学元件的模块（2）的动力传递装置，动力传递装置包括具有水平部分的第一连杆 （22），以及从所述水平部的一侧端部向与所述模块的摆动动作的轨迹一致的角度向上突出的倾斜部，以及包括水平方向的第二连杆（21） （29）和从所述水平部分的相对端部向上突出的一对平行部分（30）和（31），使得所述第二连杆沿着所述第一连杆以处于所述水平部分之间的状态互锁 第一连杆和模块，其中联锁轴（28）通过轴与第一连杆的倾斜部分连接，并且该对平行部分安装到模块的下侧 e在水平方向与轴。

公开(公告)号：US20090103625A1

公开(公告)日：2009-04-23

申请号：US12252734

申请日：2008-10-16

Applicant: Suk Ho Lee ,  Kyoung Seon Shin ,  Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Suk Ho Lee ,  Kyoung Seon Shin ,  Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/26

CPC classification number: H04N19/436

Abstract: A video encoding apparatus and method using a pipeline technique with a variable time slot are provided. More particularly, a video encoding apparatus and method capable of shortening a video encoding time by variably adjusting lengths of time slots when an H.264 video encoding process is performed in a pipeline structure are provided. The video encoding apparatus includes a plurality of functional blocks that perform video encoding steps based on an H.264 standard for macroblocks configuring input digital video signals in a pipeline structure, and a controller that controls lengths of time slots configuring the pipeline structure based on done signals received from the plurality of functional blocks. Lengths of time slots can be adjusted according to operation times of video encoding steps using done signals generated from functional blocks, thereby preventing unnecessary power consumption and delays when using a fixed-length time slot.

Abstract translation: 提供了使用具有可变时隙的流水线技术的视频编码装置和方法。 更具体地说，提供了一种视频编码装置和方法，其能够在流水线结构中执行H.264视频编码处理时，通过可变地调整时隙的长度来缩短视频编码时间。 视频编码装置包括：多个功能块，其基于用于在流水线结构中配置输入数字视频信号的宏块的H.264标准执行视频编码步骤;以及控制器，其基于完成来控制配置流水线结构的时隙的长度 从多个功能块接收的信号。 可以根据从功能块产生的完成信号的视频编码步骤的操作时间来调整时隙长度，从而在使用固定长度的时隙时防止不必要的功耗和延迟。

公开(公告)号：US06870434B2

公开(公告)日：2005-03-22

申请号：US10464735

申请日：2003-06-19

Applicant: Jin Ho Han ,  Myung Shin Kwark ,  Jong Dae Kim

Inventor： Jin Ho Han ,  Myung Shin Kwark ,  Jong Dae Kim

IPC: H03B5/32 ,  H03B5/04 ,  H03B5/36 ,  H03L1/02

CPC classification number: H03L1/026

Abstract: The present invention relates to a method for compensating temperature in a crystal oscillator including a capacitor array consisted of a first bank of unit capacitors each with low capacitance and a second bank of unit capacitors each with high capacitance. The method comprising the steps of calculating memory address that stores information about the capacitor array address in accordance with the temperature that is subtracted from present temperature by a temperature offset code; reading data from a memory address corresponding to remain bits excepted lowest bit when the lowest bit is 0 among the memory address; averaging data read from a memory address corresponding to remain bits excepted lowest bit and data of a memory address incremented by 1 from the memory address when the lowest bit is 1 among the memory address; transmitting data read from the memory address or averaged data to the first bank or second bank by comparing the memory address and temperature boundary code; and adjusting the capacitor array with capacitance corresponding to a present temperature by using data transmitted to the first bank or second bank.

Abstract translation: 本发明涉及一种用于补偿晶体振荡器中的温度的方法，该晶体振荡器包括由具有低电容的第一组单位电容器组成的电容器阵列和具有高电容的第二组单位电容器。 该方法包括以下步骤：根据从当前温度减去温度偏移代码的温度计算存储关于电容器阵列地址的信息的存储器地址; 从存储器地址中的最低位为0时，从与除了最低位之外的保持位相对应的存储器地址读取数据; 从存储器地址中的最低位为1时，从存储器地址递增1的存储器地址中除了除了最低位之外的保留位和存储器地址的数据读取的平均数据; 通过比较存储器地址和温度边界码，将从存储器地址读取的数据或平均数据发送到第一存储体或第二存储体; 以及通过使用发送到第一存储体或第二存储体的数据来调整电容器阵列与对应于当前温度的电容。

公开(公告)号：US08514937B2

公开(公告)日：2013-08-20

申请号：US12861118

申请日：2010-08-23

Applicant: Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jin Ho Han ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04N7/50

CPC classification number: H04N19/53 ,  H04N19/194 ,  H04N19/43 ,  H04N19/433 ,  H04N19/61

Abstract: There is provided a video encoding apparatus allowing for enhanced video encoding speed according to the H.264 video coding standard. The video encoding apparatus allows the memories included in the video encoding apparatus to be shared by a plurality of elements through the rearrangement and the structural change of the memories considering an efficient hierarchical motion estimation algorithm. Therefore, the video encoding apparatus has the effects of reducing the amount of transmitted and received data between the frame memory and the video encoding apparatus and enhancing video encoding speed.

Abstract translation: 提供了根据H.264视频编码标准允许增强的视频编码速度的视频编码装置。 视频编码装置允许考虑到有效的分级运动估计算法，通过重排和存储器的结构变化，包括在视频编码装置中的存储器被多个元件共享。 因此，视频编码装置具有减少帧存储器和视频编码装置之间的发送和接收数据量并提高视频编码速度的效果。

公开(公告)号：US08139643B2

公开(公告)日：2012-03-20

申请号：US12191733

申请日：2008-08-14

Applicant: Jin Ho Han ,  Suk Ho Lee ,  Seong Mo Park ,  Nak Woong Eum

Inventor： Jin Ho Han ,  Suk Ho Lee ,  Seong Mo Park ,  Nak Woong Eum

IPC: H04B1/66

CPC classification number: H04N19/523 ,  H04N19/43

Abstract: Provided is a motion estimation apparatus for moving picture coding. The apparatus includes a 1-pel buffer for storing 1-pel unit pixels using luminance signals of a reference frame which correspond to macroblocks of a current frame, a 1-pel estimator for calculating 1-pel unit motion vectors and minimum costs in correspondence to the macroblocks of the current frame and the pixels stored in the 1-pel buffer, a ½-pel interpolator for performing ½-pel unit interpolation using the pixels stored in the 1-pel buffer, a ½-pel buffer for storing the ½-pel unit interpolated pixels, a ½-pel estimator for calculating ½-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ½-pel buffer, the values calculated by the 1-pel estimator, and the macroblocks of the current frame, a ¼-pel interpolator for performing ¼-pel unit interpolation using the pixels stored in the ½-pel and 1-pel buffers, a ¼-pel buffer for storing the ¼-pel unit interpolated pixels, and a ¼-pel estimator for calculating ¼-pel unit motion vectors and minimum costs in correspondence to the pixels stored in the ¼-pel buffer, the values calculated by the ½-pel estimator, and the macroblocks of the current frame.

Abstract translation: 提供了一种用于运动图像编码的运动估计装置。 该装置包括：1个像素缓冲器，用于使用与当前帧的宏块相对应的参考帧的亮度信号来存储1个像素单位像素; 1像素估计器，用于计算1像素单位运动矢量，并对应于最小成本 当前帧的宏块和存储在1-像素缓冲器中的像素，1/2像素内插器，用于使用存储在1-像素缓冲器中的像素进行1/2像素单位内插;½像素缓冲器，用于存储1/2像素缓冲器， 像素单位内插像素，用于计算1/2像素单位运动矢量的1/2像素估计器和对应于存储在1/2像素缓冲器中的像素的最小成本，由1-像素估计器计算的值和当前的宏块 帧，¼贝尔内插器，用于使用存储在1/2贝尔和1贝尔缓冲器中的像素执行1/4贝尔单位内插，用于存储1/4倍率单位内插像素的1/4贝尔缓冲器，以及1/4贝尔估计器 用于计算¼像素单位运动矢量 对应于存储在1/4贝尔缓冲器中的像素的最小成本，由1/2贝尔估计器计算的值和当前帧的宏块。

公开(公告)号：US07432768B2

公开(公告)日：2008-10-07

申请号：US10572901

申请日：2004-06-22

Applicant: Seon Ho Han ,  Jin Ho Han ,  Mun Yang Park

Inventor： Seon Ho Han ,  Jin Ho Han ,  Mun Yang Park

IPC: H03L7/00

CPC classification number: H03B5/1841 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1265 ,  H03B5/1293

Abstract: Provided are a voltage controlled digital analog oscillator and a frequency synthesizer using the same, the oscillator comprising an oscillator having a frequency of an output signal being determined by a voltage inputted to an analog input end and a digital value inputted to a digital input end; and a digital tuner for comparing the voltage inputted to the analog input end to first and second threshold voltages and changing the digital value inputted to the digital input end according to the result, whereby it is possible to obtain a broadband frequency output with less noise.

Abstract translation: 提供一种电压控制数字模拟振荡器和使用该振荡器的频率合成器，该振荡器包括具有由输入到模拟输入端的电压和输入到数字输入端的数字值确定输出信号频率的振荡器; 以及数字调谐器，用于将输入到模拟输入端的电压与第一和第二阈值电压进行比较，并根据结果改变输入到数字输入端的数字值，由此可以获得具有较小噪声的宽带频率输出。