公开(公告)号：US20120065741A1

公开(公告)日：2012-03-15

申请号：US12880502

申请日：2010-09-13

申请人： Chao-Fu Chang ,  Kent Kuohua Chang

发明人： Chao-Fu Chang ,  Kent Kuohua Chang

IPC分类号： A61F2/02

CPC分类号： A61C8/0006 ,  A61L31/005 ,  A61L31/146

摘要： A guided tissue regeneration membrane has a top surface, a bottom surface and a plurality of through holes formed through the top and bottom surfaces. Each of the plurality of through holes has a base opening on the top surface and a tip opening on the bottom surface. The diameter of the base opening is larger than that of the tip opening. The guided tissue regeneration membrane is placed between a hard tissue and a soft tissue of gums with the top surface thereof facing the hard tissue so as to hinder the soft tissue from rapidly growing. The tip openings are available for the soft tissue to supply nutrient to the hard tissue therethrough. The hard tissue can grow from the base openings, through the corresponding through holes and to the soft tissue to repair periodontal tissue.

摘要翻译： 引导组织再生膜具有顶表面，底表面和穿过顶表面和底表面形成的多个通孔。 多个通孔中的每一个在顶表面上具有基部开口，在底面上具有顶端开口。 基座开口的直径大于顶端开口的直径。 引导组织再生膜置于硬组织和牙龈软组织之间，其顶表面面向硬组织，以阻止软组织迅速生长。 尖端开口可用于软组织，以通过其中的硬组织提供营养。 硬组织可以从基底开口，通过相应的通孔和软组织生长，以修复牙周组织。

公开(公告)号：US06706612B2

公开(公告)日：2004-03-16

申请号：US10064370

申请日：2002-07-08

申请人： Szu-Tsun Ma ,  Kent Kuohua Chang

发明人： Szu-Tsun Ma ,  Kent Kuohua Chang

IPC分类号： H01L2176

CPC分类号： H01L21/76224

摘要： A method for fabricating a shallow trench isolation structure includes forming a hard mask layer over a substrate. An ion bombardment step is further performed on the surface of the hard mask layer, followed by forming a patterned photoresist layer on the surface of the hard mask layer. Thereafter, the hard mask layer is patterned using the photoresist layer as an etching mask. An etching process is further performed to form a trench in the substrate. The photoresist layer is then removed, followed by filling an insulation layer in the trench. After this, the hard mask is removed to complete the fabrication of a shallow trench isolation region.

摘要翻译： 一种用于制造浅沟槽隔离结构的方法包括在衬底上形成硬掩模层。 在硬掩模层的表面上进一步进行离子轰击步骤，然后在硬掩模层的表面上形成图案化的光致抗蚀剂层。 此后，使用光致抗蚀剂层作为蚀刻掩模来对硬掩模层进行图案化。 进一步进行蚀刻工艺以在衬底中形成沟槽。 然后去除光致抗蚀剂层，然后在沟槽中填充绝缘层。 之后，去除硬掩模以完成浅沟槽隔离区的制造。

公开(公告)号：US06599801B1

公开(公告)日：2003-07-29

申请号：US10178524

申请日：2002-06-25

申请人： Kent Kuohua Chang ,  Erh-Kun Lai

发明人： Kent Kuohua Chang ,  Erh-Kun Lai

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A method of fabricating NROM memory cell, wherein the NROM device comprises a memory array and a peripheral portion. The fabricating method comprising the steps of: providing a substrate which a oxide layer is formed thereon; forming a peripheral polysilicon layer on the oxide layer; defining a patterned peripheral polysilicon; forming an ONO layer over the substrate in the memory array and the peripheral portion; forming an array polysilicon layer on the ONO layer; and defining a patterned array polysilicon. The method of fabricating NROM memory cell according to the invention can solve the problems of top oxide loss, touch between nitride and polysilicon, and BD over-diffusion.

摘要翻译： 一种制造NROM存储单元的方法，其中NROM器件包括存储器阵列和外围部分。 该制造方法包括以下步骤：提供在其上形成氧化物层的衬底; 在所述氧化物层上形成外围多晶硅层; 限定图案化的外围多晶硅; 在存储器阵列和周边部分中的衬底上形成ONO层; 在ONO层上形成阵列多晶硅层; 并且限定图案化阵列多晶硅。 根据本发明的制造NROM存储单元的方法可以解决顶部氧化物损失，氮化物和多晶硅之间的接触以及BD过度扩散的问题。

公开(公告)号：US06580639B1

公开(公告)日：2003-06-17

申请号：US09372406

申请日：1999-08-10

申请人： Yue-Song He ,  Kent Kuohua Chang ,  Allen U. Huang

发明人： Yue-Song He ,  Kent Kuohua Chang ,  Allen U. Huang

IPC分类号： G11C1604

CPC分类号： H01L29/66575 ,  G11C16/0483 ,  H01L21/26506 ,  H01L21/26513 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78

摘要： The present invention makes use of ion bombardment to amorphize the source and drain regions of a short channel FET prior to implanting. The source/drain implants are then localized to a shallow depth by appropriate choice of implanting conditions, typically employing rather low bombardment voltages of approximately 10 KeV. Amorphous source/drain regions substantially hinder the diffusion of source/drain dopants and thereby reduce the possibility of punchthrough and loss of FET function. Such devices are preferably used in NAND type flash memory devices maintaining proper self-boosting voltages and FET functions even when short channel lengths are employed.

摘要翻译： 本发明利用离子轰击在植入之前使短沟道FET的源极和漏极区域非晶化。 然后通过适当选择植入条件将源极/漏极植入物定位到浅深度，通常采用约10KeV的相当低的轰击电压。 无定形源极/漏极区域基本上阻碍了源极/漏极掺杂剂的扩散，从而降低了FET功能的穿透和损失的可能性。 这种器件优选地用于NAND型闪速存储器件中，即使采用短沟道长度，它们也保持适当的自增强电压和FET功能。

公开(公告)号：US06566203B2

公开(公告)日：2003-05-20

申请号：US09682341

申请日：2001-08-22

申请人： Kent Kuohua Chang ,  Samuel Cheng-Sheng Pan

发明人： Kent Kuohua Chang ,  Samuel Cheng-Sheng Pan

IPC分类号： H01L218234

CPC分类号： H01L21/26586 ,  H01L21/2652 ,  H01L21/3144 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/1083

摘要： A method for preventing electron secondary injection in a pocket implantation process performed on a nitride read only memory (NROM). The NROM has an oxide-nitride-oxide (ONO) layer formed on a silicon substrate. A plurality of bit line masks, arranged in a column, is formed on the surface of the ONO layer. A plurality of N type bit lines is formed in a region of the substrate not covered by the bit line masks. The method starts by performing a pocket implantation process of Indium ions with low energy, high dosage and using an angle nearly parallel to the ONO layer, so as to prevent electron secondary injection. Also, a plurality of P-type ultra-shallow junctions is formed in the region of the substrate not covered by the bit line masks.

公开(公告)号：US06548425B2

公开(公告)日：2003-04-15

申请号：US09851570

申请日：2001-05-10

申请人： Kent Kuohua Chang ,  Uway Tseng

发明人： Kent Kuohua Chang ,  Uway Tseng

IPC分类号： H01L2131

CPC分类号： H01L21/02238 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/11568 ,  Y10S438/954

摘要： The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

公开(公告)号：US06455890B1

公开(公告)日：2002-09-24

申请号：US09945795

申请日：2001-09-05

申请人： Kent Kuohua Chang ,  Jen-Yuan Chiu

发明人： Kent Kuohua Chang ,  Jen-Yuan Chiu

IPC分类号： H01L29788

CPC分类号： H01L21/28273 ,  H01L29/42324 ,  H01L29/4916

摘要： A structure of fabricating high gate performance for NROM technology. The method at least includes the following steps. First of all, a tunnel oxide layer on the silicon substrate. Then, a amorphous silicon layer on the tunnel oxide layer, and a poly-SiGe layer (a polysilicon layer with doped germanium) on the amorphous silicon layer. Next, an interpoly dielectric layer on the poly-SiGe layer. Finally, a polysilicon layer on the interpoly dielectric layer.

摘要翻译： NROM技术制造高栅极性能的结构。 该方法至少包括以下步骤。 首先，硅衬底上的隧道氧化物层。 然后，在非晶硅层上形成隧道氧化物层上的非晶硅层和多晶硅层（掺杂有锗的多晶硅层）。 接下来，在多晶硅层上的多层介电层。 最后，在多聚电介质层上的多晶硅层。

公开(公告)号：US06448136B1

公开(公告)日：2002-09-10

申请号：US09777231

申请日：2001-02-05

申请人： Kent Kuohua Chang ,  Cheng-Chen Calvin Hsueh

发明人： Kent Kuohua Chang ,  Cheng-Chen Calvin Hsueh

IPC分类号： H01L218247

CPC分类号： H01L21/28017 ,  H01L21/28273 ,  Y10S438/908

摘要： A method of manufacturing flash memory. The method includes using a single wafer consecutive system process. A silicon wafer is placed inside one of the reaction chambers of a chemical vapor deposition station. Tunneling oxide layer, silicon nitride floating gate, silicon oxide layer and control gate are simultaneously formed over wafers inside the station. Breaking the vacuum inside the station and cleaning the wafer are unnecessary between various processing steps.

摘要翻译： 一种制造闪存的方法。 该方法包括使用单个晶片连续系统过程。 将硅晶片放置在化学气相沉积站的一个反应室内。 隧道内氧化物层，氮化硅浮栅，氧化硅层和控制栅极同时形成在工位内的晶片上。 在各种处理步骤之间，不需要打破车站内的真空并清洁晶片。

公开(公告)号：US06300658B1

公开(公告)日：2001-10-09

申请号：US09368073

申请日：1999-08-03

申请人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

发明人： John JianShi Wang ,  Kent Kuohua Chang ,  Hao Fang ,  Lu You

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76837 ,  H01L27/115

摘要： The present invention provides a method for reducing the gate aspect ratio of a flash memory device. The method includes forming a tunnel oxide layer on a substrate; forming a polysilicon layer on the tunnel oxide layer; forming an insulating layer on the polysilicon layer; forming a control gate layer on the polysilicon layer; etching at least the tunnel oxide layer, the insulating layer, and the control gate layer to form at least two stack structures; forming a plurality of spacers at sides of the at least two stack structures; and filling at least one gap between the at least two stack structures with an oxide, where the control gate layer provides a gate aspect ratio which allows for a maximum step coverage by the oxide. In a preferred embodiment, the method uses nickel silicide instead of the conventional tungsten silicide in the control gate layers of the cells of the device. Nickel silicide has higher conductivity than conventional silicides, thus a thinner layer of nickel silicide may be used without sacrificing performance. Nickel silicide also has a lower barrier height for holes, thus maintaining a low contact resistance. With a thinner nickel silicide layer, the gate aspect ratio of the cells are lowered, allowing for a maximum step coverage by the gap-filling oxide. The reliability of the device is thus improved.

摘要翻译： 本发明提供一种降低闪速存储器件的栅极纵横比的方法。 该方法包括在衬底上形成隧道氧化物层; 在隧道氧化层上形成多晶硅层; 在所述多晶硅层上形成绝缘层; 在所述多晶硅层上形成控制栅极层; 至少蚀刻隧道氧化物层，绝缘层和控制栅极层以形成至少两个堆叠结构; 在所述至少两个堆叠结构的侧面处形成多个间隔物; 以及用所述氧化物填充所述至少两个堆叠结构之间的至少一个间隙，其中所述控制栅极层提供允许所述氧化物的最大阶跃覆盖的栅极纵横比。 在优选实施例中，该方法在装置的电池的控制栅极层中使用硅化镍代替常规的硅化钨。 硅化镍具有比常规硅化物更高的导电性，因此可以使用更薄的硅化镍层而不牺牲性能。 硅化镍也具有较低的孔的阻挡高度，因此保持低的接触电阻。 利用更薄的硅化镍层，电池的栅极纵横比降低，允许通过间隙填充氧化物的最大阶梯覆盖。 因此提高了装置的可靠性。

公开(公告)号：US06235586B1

公开(公告)日：2001-05-22

申请号：US09352801

申请日：1999-07-13

申请人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

发明人： Kenneth Wo-Wai Au ,  Kent Kuohua Chang ,  Hao Fang

IPC分类号： H01L218247

CPC分类号： H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524

摘要： In one embodiment, the present invention relates to a method of forming a NAND type flash memory device, involving the steps of growing a first oxide layer over at least a portion of a substrate, the substrate including a flash memory cell area and a select gate area; removing a portion of the first oxide layer in the flash memory cell area of the substrate; growing a second oxide layer over at least a portion of the substrate in the flash memory cell area and over at least a portion of the a first oxide layer in the select gate area; depositing a first in situ doped amorphous silicon layer over at least a portion of the second oxide layer, the first in situ doped amorphous silicon layer having a thickness from about 400 Å to about 1,000 Å; depositing a dielectric layer over at least a portion of the first in situ doped amorphous silicon layer; depositing a second doped amorphous silicon layer over at least a portion of the dielectric layer; and forming a flash memory cell in the flash memory cell area of the substrate and a select gate transistor in the select gate area substrate, the flash memory cell comprising the second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer, and the select gate transistor comprising the first oxide layer, second oxide layer, the first in situ doped amorphous silicon layer, the dielectric layer, and the second doped amorphous silicon layer.

摘要翻译： 在一个实施例中，本发明涉及一种形成NAND型快闪存储器件的方法，包括以下步骤：在衬底的至少一部分上生长第一氧化物层，所述衬底包括闪存单元区域和选择栅极 区; 去除衬底的闪存单元区域中的第一氧化物层的一部分; 在所述闪存单元区域中的所述衬底的至少一部分上以及所述选择栅极区域中的所述第一氧化物层的至少一部分上生长第二氧化物层; 在所述第二氧化物层的至少一部分上沉积第一原位掺杂的非晶硅层，所述第一原位掺杂的非晶硅层具有从约至在的厚度; 在第一原位掺杂的非晶硅层的至少一部分上沉积介电层; 在所述电介质层的至少一部分上沉积第二掺杂非晶硅层; 以及在所述衬底的所述闪存单元区域中形成快闪存储器单元，以及在所述选择栅极区域衬底中形成选择栅极晶体管，所述闪存单元包括所述第二氧化物层，所述第一原位掺杂非晶硅层，所述介电层， 和第二掺杂非晶硅层，选择栅晶体管包括第一氧化物层，第二氧化物层，第一原位掺杂非晶硅层，介电层和第二掺杂非晶硅层。