公开(公告)号：US08946825B2

公开(公告)日：2015-02-03

申请号：US13433194

申请日：2012-03-28

申请人： David Yen ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

发明人： David Yen ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC分类号： H01L23/62

CPC分类号： H01L27/0928 ,  H01L21/263 ,  H01L21/823871 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0629 ,  H01L29/6609

摘要： During various processing operations, ions from process plasma may be transfer to a deep n-well (DNW) formed under devices structures. A reverse-biased diode may be connected to the signal line to protect a gate dielectric formed outside the DNW and is connected to the drain of the transistor formed inside the DNW.

摘要翻译： 在各种处理操作期间，来自工艺等离子体的离子可以转移到在器件结构下形成的深n阱（DNW）。 反向偏置二极管可以连接到信号线以保护形成在DNW外部的栅极电介质，并且连接到形成在DNW内部的晶体管的漏极。

公开(公告)号：US08929154B2

公开(公告)日：2015-01-06

申请号：US13267235

申请日：2011-10-06

申请人： Jacklyn Chang ,  Derek C. Tao ,  Yukit Tang ,  Kuoyuan (Peter) Hsu

发明人： Jacklyn Chang ,  Derek C. Tao ,  Yukit Tang ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C7/10 ,  G11C7/18 ,  H01L27/02 ,  G11C11/412 ,  G11C11/413 ,  H01L27/11

CPC分类号： G11C7/18 ,  G11C11/412 ,  G11C11/413 ,  H01L27/0207 ,  H01L27/1104

摘要： A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.

摘要翻译： 半导体结构包括第一带状电池，第一读取端口和第一VSS端子。 第一带状电池具有第一带电池VSS区域。 第一读取端口具有第一读取端口VSS区域，第一读取端口读取位线区域和第一读取端口聚合区域。 第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。

公开(公告)号：US08767498B2

公开(公告)日：2014-07-01

申请号：US13285357

申请日：2011-10-31

申请人： Jiann-Tseng Huang ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

发明人： Jiann-Tseng Huang ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C17/14

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A circuit includes a fuse circuit and a control circuit. The fuse circuit has an electrical fuse. The control circuit is configured to receive an input signal having an input pulse, and, based on a feedback signal from the fuse circuit, generates a read pulse smaller than the input pulse for use in reading the data stored in the electrical fuse.

摘要翻译： 电路包括熔丝电路和控制电路。 保险丝电路具有电熔丝。 控制电路被配置为接收具有输入脉冲的输入信号，并且基于来自熔丝电路的反馈信号，产生比用于读取存储在电熔丝中的数据的输入脉冲更小的读取脉冲。

公开(公告)号：US08704376B2

公开(公告)日：2014-04-22

申请号：US13443467

申请日：2012-04-10

申请人： Jacklyn Chang ,  Evan Yong Zhang ,  Derek C. Tao ,  Kuoyuan (Peter) Hsu

发明人： Jacklyn Chang ,  Evan Yong Zhang ,  Derek C. Tao ,  Kuoyuan (Peter) Hsu

IPC分类号： H01L23/498

CPC分类号： H01L27/1104 ,  H01L27/0207

摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.

摘要翻译： 布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。 井在底层。 第一多晶硅区位于第一掺杂区和第二掺杂区之间。 第二聚合区位于第三掺杂区和第四掺杂区之间。 第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。 第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。 阱被配置为用作晶体管的体积并从第二电源接收第二电压值。

公开(公告)号：US08692580B2

公开(公告)日：2014-04-08

申请号：US13407548

申请日：2012-02-28

申请人： Chen-Ming Hung ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

发明人： Chen-Ming Hung ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC分类号： H03K3/00

CPC分类号： G01R27/08 ,  G11C7/062 ,  G11C17/18 ,  G11C2207/063 ,  H03F3/45179 ,  H03F2200/555 ,  H03F2203/45394 ,  H03F2203/45674

摘要： An amplifying circuit comprises a bias circuit, a reference circuit, a first circuit, and an amplifying sub-circuit. The bias circuit is configured to provide a bias current. The reference circuit is configured to provide a first differential input based on a reference resistive device and a reference current derived from the bias current. The first circuit is configured to provide a second differential input based on a first current and a first resistance. The amplifying sub-circuit is configured to receive the first differential input and the second differential input and to generate a sense amplifying output indicative of a resistance relationship between the first resistance and a resistance of the reference resistive device.

摘要翻译： 放大电路包括偏置电路，参考电路，第一电路和放大子电路。 偏置电路被配置为提供偏置电流。 参考电路被配置为提供基于参考电阻器件的第一差分输入和从偏置电流导出的参考电流。 第一电路被配置为基于第一电流和第一电阻提供第二差分输入。 放大子电路被配置为接收第一差分输入和第二差分输入，并且产生指示第一电阻和参考电阻器件的电阻之间的电阻关系的读出放大输出。

公开(公告)号：US07557642B2

公开(公告)日：2009-07-07

申请号：US11845628

申请日：2007-08-27

申请人： Kuoyuan (Peter) Hsu ,  Maofeng Len

发明人： Kuoyuan (Peter) Hsu ,  Maofeng Len

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： A system and a method is disclosed for allowing bandgap circuitry to function on a low supply voltage integrated circuit, and for using the reference voltage (Vbg) generated by the bandgap circuitry to enable a reference voltage to control system voltage. An illustrative embodiment comprises a charge pump to raise a supply voltage to a system voltage, and an open loop controller, which provides a first signal to activate the charge pump, enabling a bandgap circuit, which outputs a bandgap voltage reference. Further, the system comprises a closed loop controller, which regulates the system voltage by comparing the system voltage to the bandgap reference voltage. Upon the system voltage falling below a target voltage, the closed loop controller provides a second signal to activate the charge pump. Additionally the system comprises a switch controller, which selects the closed loop controller upon sensing the bandgap circuit is active.

摘要翻译： 公开了一种用于允许带隙电路在低电源电压集成电路上工作并且使用由带隙电路产生的参考电压（Vbg）使得参考电压能够控制系统电压的系统和方法。 示例性实施例包括用于提高系统电压的电源电压的电荷泵和提供第一信号以激活电荷泵的开环控制器，其实现输出带隙电压基准的带隙电路。 此外，该系统包括闭环控制器，其通过将系统电压与带隙参考电压进行比较来调节系统电压。 当系统电压低于目标电压时，闭环控制器提供第二信号以激活电荷泵。 另外，该系统包括开关控制器，其在感测带隙电路有效时选择闭环控制器。

公开(公告)号：US20080117698A1

公开(公告)日：2008-05-22

申请号：US11807520

申请日：2007-05-29

申请人： Kuoyuan (Peter) Hsu

发明人： Kuoyuan (Peter) Hsu

IPC分类号： G11C7/06

CPC分类号： G11C11/4076 ,  G11C11/4097

摘要： An architecture, circuit and method for providing a high speed operation DRAM memory with reduced cell disturb. A DRAM global bit line select circuit couples a pair of local bit lines and the associated sense amplifier to the global bit lines using a circuit optimized for high speed operation. The select circuit and method also reduces or eliminates the bit line disturb effect of the prior art. The circuit and architecture of the DRAM incorporating the select circuit is particularly useful for embedding DRAM memory with other logic in an integrated circuit. For a read operation the select circuit discharges the appropriate global bit line directly to ground thus speeding the read cycles. For a write operation, a dedicated control line is used to couple write data to from the global bit lines to the selected local bit lines. Methods for operating the DRAM and the select circuits are disclosed.

摘要翻译： 一种用于提供具有减少的信元干扰的高速操作DRAM存储器的架构，电路和方法。 DRAM全局位线选择电路使用针对高速操作优化的电路将一对局部位线和相关读出放大器耦合到全局位线。 选择电路和方法还减少或消除了现有技术的位线干扰效应。 结合选择电路的DRAM的电路和架构对于在集成电路中嵌入具有其他逻辑的DRAM存储器是特别有用的。 对于读操作，选择电路将适当的全局位线直接放电到地，从而加速读周期。 对于写入操作，专用控制线用于将写入数据从全局位线耦合到所选择的本地位线。 公开了用于操作DRAM和选择电路的方法。

公开(公告)号：US09135099B2

公开(公告)日：2015-09-15

申请号：US13434588

申请日：2012-03-29

申请人： Yun-Han Chen ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

发明人： Yun-Han Chen ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  H03M13/19 ,  H03M13/00

CPC分类号： G06F11/073 ,  G06F11/0793 ,  G06F11/1008 ,  H03M13/19 ,  H03M13/6561

摘要： A method includes, by a first circuit, converting a plurality of bits in a first format to a second format. The plurality of bits in the second format is used, by a second circuit, to program a plurality of memory cells corresponding to the plurality of bits. The first format is a parallel format. The second format is a serial format. The first circuit and the second circuit are electrically coupled together in a chip. In some embodiments, the plurality of bits includes address information, cell data information, and program information of a memory cell that has an error. In some embodiments, the plurality of bits includes word data information of a word and error code and correction information corresponding to the word data information of the word.

摘要翻译： 一种方法包括通过第一电路将第一格式的多个比特转换成第二格式。 通过第二电路使用第二格式的多个比特来对与多个比特相对应的多个存储单元进行编程。 第一种格式是并行格式。 第二种格式是串行格式。 第一电路和第二电路在芯片中电耦合在一起。 在一些实施例中，多个位包括地址信息，单元数据信息和具有错误的存储器单元的程序信息。 在一些实施例中，多个比特包括单词的字数据信息和与单词的单词数据信息对应的错误代码和校正信息。

公开(公告)号：US08760955B2

公开(公告)日：2014-06-24

申请号：US13278686

申请日：2011-10-21

申请人： Wei-Li Liao ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

发明人： Wei-Li Liao ,  Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu

IPC分类号： G11C17/16

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A mechanism of reconfiguring an eFuse memory array to have two or more neighboring eFuse bit cells placed side by and side and sharing a program bit line. By allowing two or more neighboring eFuse bit cells to share a program bit line, the length of the program bit line is shortened, which results in lower resistivity of the program bit line. The width of the program bit line may also be increased to further reduce the resistivity of program bit line. Program bit lines with low resistance and high current are needed for advanced eFuse memory arrays using low-resistivity eFuses.

摘要翻译： 重新配置eFuse存储器阵列以使两个或更多个相邻的eFuse位单元被放置在旁边并共享一个程序位线的机制。 通过允许两个或多个相邻的eFuse位单元共享程序位线，程序位线的长度被缩短，这导致程序位线的电阻较低。 也可以增加编程位线的宽度，以进一步降低程序位线的电阻率。 使用低电阻率eFuse的高级eFuse存储器阵列需要具有低电阻和高电流的程序位线。

公开(公告)号：US08614927B2

公开(公告)日：2013-12-24

申请号：US13595551

申请日：2012-08-27

申请人： Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  Wei-Li Liao

发明人： Sung-Chieh Lin ,  Kuoyuan (Peter) Hsu ,  Jiann-Tseng Huang ,  Wei-Li Liao

IPC分类号： G11C7/00

CPC分类号： G11C8/12 ,  G11C17/18

摘要： This description relates to a circuit including a bit line. The circuit further includes at least one memory bank. The at least one memory bank includes at least one memory cell, a first device configured to provide a current path between the bit line and the at least one memory cell when the at least one memory cell is activated, and a second device configured to reduce current leakage between the bit line and the at least one memory cell when the at least one memory cell is deactivated. The circuit further includes a tracking device configured to receive a mirror current substantially equal to a current along the current path, the tracking device configured to have a resistance substantially equal to a cumulative resistance of all memory cells of the at least one memory cell.

摘要翻译： 本说明书涉及包括位线的电路。 电路还包括至少一个存储体。 所述至少一个存储体包括至少一个存储单元，配置为当所述至少一个存储单元被激活时在所述位线和所述至少一个存储器单元之间提供电流路径的第一设备，以及被配置为减少 当所述至少一个存储器单元被停用时，所述位线与所述至少一个存储器单元之间的电流泄漏。 电路还包括跟踪装置，其被配置为接收基本上等于沿着电流路径的电流的反射镜电流，跟踪装置被配置为具有基本上等于至少一个存储器单元的所有存储器单元的累积电阻的电阻。