公开(公告)号：US5630171A

公开(公告)日：1997-05-13

申请号：US667914

申请日：1996-06-20

申请人： Edward J. Chejlava, Jr. ,  Leslie E. Cline ,  Kenneth C. Curt

发明人： Edward J. Chejlava, Jr. ,  Leslie E. Cline ,  Kenneth C. Curt

IPC分类号： G06F13/12 ,  G06F3/06 ,  G06F13/36 ,  G06F13/38 ,  G06F13/00

CPC分类号： G06F3/0601 ,  G06F13/385 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0689 ,  G06F2003/0692 ,  G06F3/0638 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s) uses a pipelined architecture to increase the use of the available data transfer bandwidth. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. The LBPI maintains a countdown of the number of words of a data sector already transferred and/or "snoops" the peripheral device commands from the computer to predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.

摘要翻译： 用于计算机本地总线的高性能本地总线外设接口（LBPI）及其高性能外设接口使用流水线架构来增加可用数据传输带宽的使用。 在一个实施例中，LBPI可以可选择地配置成在主机侧耦合到VL总线或PCI总线。 LBPI维护已经传送的数据扇区的字数和/或从计算机“窥探”外围设备命令的倒数，以预测后续读取数据传输命令的发生。 控制状态机还“窥探”外围设备命令以保持其对外围设备的操作参数的记录，并且还跟踪哪些设备当前处于活动状态。 在一个实施例中，LBPI支持外围方面的DMA和PIO数据传输。 在另一个实施例中，LBPI将存储器数据传输转换成IO数据传输以提高IO数据传输的效率。 在DMA模式数据传输操作期间使用DMA超时计数器，以防止系统无限期地等待来自所选外设的适当的DMA请求信号。 在DMA模式数据传输操作期间，可以产生强制中断并将其发送到主机以便模拟PIO模式数据传送操作。 在DMA模式数据传输操作期间，利用强制状态或“伪3F6”寄存器将状态信息传送到主机系统。

公开(公告)号：US20090193274A1

公开(公告)日：2009-07-30

申请号：US12419090

申请日：2009-04-06

申请人： Leslie E. Cline ,  Siripong Sritanyaratana ,  Alon Naveh ,  Shai Rotem ,  Eric C. Samson ,  Michael N. Derr

发明人： Leslie E. Cline ,  Siripong Sritanyaratana ,  Alon Naveh ,  Shai Rotem ,  Eric C. Samson ,  Michael N. Derr

IPC分类号： G06F1/32 ,  G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0835 ,  G06F2212/1028 ,  Y02D10/13

摘要： Systems and methods of managing power provide for placing a processor in a non-snoopable state, where the processor is associated with a system memory. One or more data transfers between a controller and the system memory can be serviced while the processor is in the non-snoopable state. In one embodiment, it is determined that the processor has flushed an internal cache of the processor to the system memory before placing the processor in the non-snoopable state.

摘要翻译： 管理电源的系统和方法提供将处理器置于不可窥探状态，其中处理器与系统存储器相关联。 当处理器处于非可窥探状态时，可以在控制器和系统存储器之间进行一个或多个数据传输。 在一个实施例中，在将处理器置于非可窥探状态之前，确定处理器将处理器的内部高速缓冲器刷新到系统存储器。

公开(公告)号：US07343502B2

公开(公告)日：2008-03-11

申请号：US10899530

申请日：2004-07-26

申请人： Eric C. Samson ,  Aditya Navale ,  Leslie E. Cline

发明人： Eric C. Samson ,  Aditya Navale ,  Leslie E. Cline

IPC分类号： G06F1/26

CPC分类号： G06F1/3225

摘要： Embodiments of the present invention provide a method and apparatus for conserving power in an electronic device. In particular, embodiments of the present invention dynamically place the memory in self-refresh and chipset clock circuits in power down mode while keeping the isochronous streams (such as display) updated and servicing bus master cycles in a power savings mode.

摘要翻译： 本发明的实施例提供了一种用于在电子设备中节省功率的方法和装置。 特别地，本发明的实施例将存储器动态地将自刷新和芯片组时钟电路放置在断电模式中，同时保持同步流（例如显示）被更新并且在节电模式下维持总线主控周期。

公开(公告)号：US07340550B2

公开(公告)日：2008-03-04

申请号：US11004011

申请日：2004-12-02

申请人： Michael N. Derr ,  John Howard ,  Darren Abramson ,  Leslie E. Cline ,  Rob Strong

发明人： Michael N. Derr ,  John Howard ,  Darren Abramson ,  Leslie E. Cline ,  Rob Strong

IPC分类号： G06F13/36 ,  G06F1/00

CPC分类号： G06F13/28 ,  G06F2213/0042 ,  Y02D10/14

摘要： A circuit for monitoring future Universal Serial Bus (USB) activities is described. Specifically, the circuit may comprise a Direct Memory Access (DMA) engine schedule prefetcher. The DMA engine schedule prefetcher accesses linked list schedule structures in main memory. The structures are checked for future frames where the linked list has USB activity scheduled. A periodic DMA engine subsequently accesses main memory only during frames where USB traffic is scheduled.

摘要翻译： 描述了用于监控未来通用串行总线（USB）活动的电路。 具体地，电路可以包括直接存储器访问（DMA）引擎调度预取器。 DMA引擎调度预取器访问主内存中的链表列表调度结构。 对结构进行检查，以便链接列表安排USB活动的将来帧。 周期性DMA引擎随后仅在安排USB流量的帧期间访问主存储器。

公开(公告)号：US06988211B2

公开(公告)日：2006-01-17

申请号：US09751528

申请日：2000-12-29

申请人： Leslie E. Cline ,  Xia Dai ,  Varghese George ,  Robert L. Farrell

发明人： Leslie E. Cline ,  Xia Dai ,  Varghese George ,  Robert L. Farrell

IPC分类号： G06F1/26

CPC分类号： G06F1/324 ,  G06F1/3203 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the various combinations will work for the particular processor device. Software can then be used to select a combination from this table, to control the actual frequency/voltage combination that is being implemented at a given time. This allows dynamic control over the power/performance tradeoff, so that the system can see maximum power savings consistent with acceptable performance, as operating and environmental considerations continue to change the most desirable selections.

摘要翻译： 可以在处理器中激活的多个时钟频率/电压电平组合的可选择控制。 一个表可以放置在硬件中，定义了CPU时钟频率和CPU工作电压的多种组合。 通过将表放置在硬件中，可以确保所有各种组合都适用于特定的处理器设备。 然后可以使用软件从该表中选择组合，以控制在给定时间正在实施的实际频率/电压组合。 这允许对功率/性能的权衡进行动态控制，使得系统可以看到与可接受的性能一致的最大功率节省，因为操作和环境考虑继续改变最理想的选择。

公开(公告)号：US06802018B2

公开(公告)日：2004-10-05

申请号：US09748921

申请日：2000-12-27

申请人： David Bormann ,  Leslie E. Cline ,  Frank Hart ,  Rudi Rughoonundon

发明人： David Bormann ,  Leslie E. Cline ,  Frank Hart ,  Rudi Rughoonundon

IPC分类号： G06F126

CPC分类号： G06F13/4068

摘要： A method and apparatus for facilitating direct access to computer resources by a peripheral device while the computer's CPU is in a sleeping state. A peripheral device having a circuit to detect the power management state of a central processor, a first interface to couple the device to the central processor if the circuit detects the first power management state, and a second interface to couple the device to a peripheral device if the circuit detects the second power management state.

摘要翻译： 一种在计算机的CPU处于睡眠状态时便于由外围设备直接访问计算机资源的方法和装置。 具有检测中央处理器的电源管理状态的电路的外围设备，如果电路检测到第一电源管理状态，则将该设备耦合到中央处理器的第一接口以及将该设备耦合到外围设备的第二接口 如果电路检测到第二电源管理状态。

公开(公告)号：US06704877B2

公开(公告)日：2004-03-09

申请号：US09751530

申请日：2000-12-29

申请人： Leslie E. Cline ,  Varghese George ,  David Wyatt

发明人： Leslie E. Cline ,  Varghese George ,  David Wyatt

IPC分类号： G06F100

CPC分类号： G06F9/30101 ,  G06F1/3203

摘要： A device controller can have multiple device performance states (DPS), which represent different levels of performance vs. power consumption during operation. The device controller can include a DPS status register that can be read by a processor, to indicate the current DPS, and a DPS control register that can be written by the processor, to change the current DPS to a desired DPS. The controller may also have a processor performance state (PPS) status register which can be used to affect the desired choice of DPS based on the performance state of the processor. Each of the registers can be accessed by the device driver for that device controller. The DPS of multiple devices can be coordinated to achieve an improved system-level reduction in power consumption, while maintaining sufficient operational capability.

摘要翻译： 设备控制器可以具有多个设备性能状态（DPS），其表示不同的性能水平与操作期间的功率消耗。 设备控制器可以包括可由处理器读取，指示当前DPS的DPS状态寄存器和可由处理器写入的DPS控制寄存器，以将当前DPS改变为期望的DPS。 控制器还可以具有处理器性能状态（PPS）状态寄存器，其可以用于基于处理器的性能状态影响DPS的期望选择。 每个寄存器都可以由该设备控制器的设备驱动程序访问。 可以协调多个设备的DPS，以在维持足够的操作能力的同时实现功率消耗的系统级降低。

公开(公告)号：US5592682A

公开(公告)日：1997-01-07

申请号：US329557

申请日：1994-10-25

申请人： Edward J. Chejlava, Jr. ,  Leslie E. Cline ,  Kenneth C. Curt

发明人： Edward J. Chejlava, Jr. ,  Leslie E. Cline ,  Kenneth C. Curt

IPC分类号： G06F13/12 ,  G06F3/06 ,  G06F13/36 ,  G06F13/38 ,  G06F15/02

CPC分类号： G06F3/0601 ,  G06F13/385 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0689 ,  G06F2003/0692 ,  G06F3/0638 ,  Y02B60/1228 ,  Y02B60/1235

摘要： A high performance Local Bus Peripheral Interface (LBPI) for a computer local bus and its high performance peripheral interface(s), using a pipelined architecture to increase the use of the available data transfer bandwidth. To accomplish the above, the LBPI, which is coupled between the computer local bus and the peripheral interface(s), is provided a pipelined architecture which includes a Read Ahead Buffer, a Read Ahead Counter, a Data Out Latch, and a Controlling State Machine with a Configuration Register. In one embodiment, the LBPI can be selectably configured to couple on the host side to either a VL bus or PCI bus. Efficiency of Read-Ahead operations is further enhanced by maintaining a countdown of the number of words of a data sector already transferred and/or "snooping" the peripheral device commands from the computer to intelligently predict the occurrence of subsequent read data transfers commands. The Controlling State Machine also "snoops" the peripheral device commands to maintain its record of the operating parameters of the peripheral devices and also keeps track of which of the devices is currently active. In one embodiment, the LBPI supports DMA and PIO data transfers on the peripheral side. In another embodiment, the LBPI translates memory data transfers into IO data transfers to improve efficiency of IO data transfers. A DMA Timeout Counter is used during DMA mode data transfer operations to prevent the system from indefinitely waiting for an appropriate DMA Request Signal from a selected peripheral. During a DMA mode data transfer operation, forced interrupts may be generated and transmitted to the host in order to emulate a PIO mode data transfer operation. During a DMA mode data transfer operation, an imposed status or "Fake 3F6" register is utilized to transmit status information to the host system.