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109 条记录 (耗时 0.04 秒)

    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF
    22.
    发明申请
    STATIC RANDOM ACCESS MEMORY APPARATUS AND BIT-LINE VOLTAGE CONTROLLER THEREOF 有权
    静态随机存取存储器和位线电压控制器

    公开(公告)号：US20140009999A1

    公开(公告)日：2014-01-09

    申请号：US13665941

    申请日：2012-11-01

    申请人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    发明人： Ching-Te Chuang ,  Nan-Chun Lien ,  Wei-Nan Liao ,  Chi-Hsin Chang ,  Hao-I Yang ,  Wei Hwang ,  Ming-Hsien Tu

    IPC分类号： G11C11/00

    CPC分类号： G11C11/413

    摘要： A static random access memory apparatus and a bit-line voltage controller thereof are disclosed. The bit-line voltage controller includes a controller, a pull-up circuit, a pull-down circuit and a voltage keeping circuit. The controller receives a bank selecting signal and a clock signal, and decides a pull-up time period, a pull-down time period and a voltage keeping time period according to the bank selecting signal and the clock signal. The pull-up circuit pulls up a bit-line power according to a first reference voltage within the pull-up time period. The pull-down circuit pulls down the bit-line power according to a second reference voltage within the pull-down time period. The voltage keeping circuit keeps the bit-line power to equal to an output voltage during the voltage keeping time period. The voltage keeping time period is after the pull-up time period and the pull-down time period.

    摘要翻译： 公开了一种静态随机存取存储器及其位线电压控制器。 位线电压控制器包括控制器，上拉电路，下拉电路和保压电路。 控制器接收存储体选择信号和时钟信号，并且根据存储体选择信号和时钟信号确定上拉时间段，下拉时间段和保持时间周期。 上拉电路在上拉时间段内根据第一个参考电压拉出位线电源。 下拉电路在下拉时间段内根据第二参考电压拉低位线电源。 电压保持电路在电压保持时间段期间将位线功率保持为等于输出电压。 电压保持时间段在上拉时间段和下拉时间段之后。

    SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY
    24.
    发明申请
    SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY 审中-公开
    用于分配高速缓存存储器的系统和方法

    公开(公告)号：US20130031327A1

    公开(公告)日：2013-01-31

    申请号：US13192856

    申请日：2011-07-28

    申请人： Yung CHANG ,  Po-Tsang Huang ,  Wei Hwang

    发明人： Yung CHANG ,  Po-Tsang Huang ,  Wei Hwang

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0811 ,  G06F12/084 ,  Y02D10/13

    摘要： Different processor elements in multi-task/multi-core system on chip may have different memory requirements at runtime. The method for adaptively allocating cache memory re-allocates the cache resource by updating the bank assignment table. According to the associativity-based partitioning scheme, centralized memory is separated into several groups of SRAM banks which are numbered differently. These groups are assigned to different processor elements to be L2 caches. The bank assignment information is recoded in bank assignment table, and is updated by system profiling engine. By changing the information in bank assignment table, the cache resource re-allocation for processor elements is achieved.

    摘要翻译： 多任务/多核系统芯片中的不同处理器元件在运行时可能具有不同的内存要求。 用于自适应地分配高速缓存的方法通过更新银行分配表来重新分配高速缓存资源。 根据基于关联性的分区方案，将集中式存储器分成若干组，这些SRAM组的编号不同。 这些组被分配到不同的处理器元素以作为L2高速缓存。 银行分配信息在银行分配表中重新编码，并由系统概要分析引擎更新。 通过改变银行分配表中的信息，实现处理器元件的缓存资源重新分配。

    Disturb-free static random access memory cell
    25.
    发明授权
    Disturb-free static random access memory cell 有权
    无噪音静态随机存取存储单元

    公开(公告)号：US08259510B2

    公开(公告)日：2012-09-04

    申请号：US12772238

    申请日：2010-05-03

    申请人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    发明人： Ching-Te Chuang ,  Hao-I Yang ,  Jihi-Yu Lin ,  Shyh-Chyi Yang ,  Ming-Hsien Tu ,  Wei Hwang ,  Shyh-Jye Jou ,  Kun-Ti Lee ,  Hung-Yu Li

    IPC分类号： G11C7/00

    CPC分类号： G11C11/412

    摘要： A disturb-free static random access memory cell includes: a latch circuit having a first access terminal and a second access terminal; a first switching circuit having a first bit transferring terminal coupled to the first access terminal, a first control terminal coupled to a first write word line, and a second bit transferring terminal; a second switching circuit having a third bit transferring terminal coupled to the second access terminal, a second control terminal coupled to a second write word line, and a fourth bit transferring terminal coupled to the second bit transferring terminal; a third switching circuit having a fifth bit transferring terminal coupled to the fourth bit transferring terminal, a third control terminal coupled to a word line, and a sixth bit transferring terminal coupled to a bit line; and a sensing amplifier coupled to the bit line, for determining a bit value appearing at the bit line.

    摘要翻译： 无干扰的静态随机存取存储单元包括：具有第一接入终端和第二接入终端的锁存电路; 第一切换电路，具有耦合到第一接入终端的第一比特传送终端，耦合到第一写字线的第一控制终端和第二比特传送终端; 第二切换电路，具有耦合到第二接入终端的第三比特传送终端，耦合到第二写字线的第二控制终端，以及耦合到第二比特传送终端的第四比特传送终端。 第三开关电路，具有耦合到第四位转移终端的第五位转移终端，耦合到字线的第三控制端和耦合到位线的第六位转移端; 以及耦合到位线的感测放大器，用于确定出现在位线处的位值。

    Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus
    26.
    发明授权
    Dual-threshold-voltage two-port sub-threshold SRAM cell apparatus 有权
    双阈值电压双端口子阈值SRAM单元设备

    公开(公告)号：US08072818B2

    公开(公告)日：2011-12-06

    申请号：US12654730

    申请日：2009-12-30

    申请人： Mu-Tien Chang ,  Po-Tsang Huang ,  Wei Hwang

    发明人： Mu-Tien Chang ,  Po-Tsang Huang ,  Wei Hwang

    IPC分类号： G11C7/00 ,  G11C8/16

    CPC分类号： G11C8/16 ,  G11C11/412

    摘要： The invention relates to a dual-threshold-voltage two-port sub-threshold SRAM cell apparatus. The above-mentioned apparatus comprises a first inverter, a second inverter, an access transistor and a read buffer. The first inverter and the second inverter include a plurality of first operating elements and a plurality of second operating elements for storing data. The access transistor is coupled to the first inverter and the second inverter, wherein the first operating elements and the second operating elements are high threshold voltage operating elements and the access transistor is low threshold voltage operating transistor. The read buffer is used for performing a read operation.

    摘要翻译： 本发明涉及双阈值电压双端口子阈值SRAM单元装置。 上述装置包括第一反相器，第二反相器，存取晶体管和读缓冲器。 第一反相器和第二反相器包括用于存储数据的多个第一操作元件和多个第二操作元件。 存取晶体管耦合到第一反相器和第二反相器，其中第一操作元件和第二操作元件是高阈值电压操作元件，并且存取晶体管是低阈值电压操作晶体管。 读缓冲器用于执行读操作。

    BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY
    27.
    发明申请
    BUTTERFLY MATCH-LINE STRUCTURE AND SEARCH METHOD IMPLEMENTED THEREBY 有权
    BUTTERFLY匹配线结构和搜索方法实现

    公开(公告)号：US20080177944A1

    公开(公告)日：2008-07-24

    申请号：US11675440

    申请日：2007-02-15

    申请人： Po-Tsang Huang ,  Wei Hwang ,  Shu-Wei Chang

    发明人： Po-Tsang Huang ,  Wei Hwang ,  Shu-Wei Chang

    IPC分类号： G06F12/00 ,  G11C15/04 ,  G06F13/00 ,  G06F13/28

    CPC分类号： G11C15/04

    摘要： The present invention discloses a butterfly match-line structure and a search method implemented thereby, wherein the parallelism of the match lines is increased to shorten the search time, and a butterfly-type connection is used to reduce the power consumption and achieve the best energy efficiency. Via the butterfly-type connection, information can be reciprocally transmitted between the parallel match lines, which are independent originally. When a miss case occurs, more succeeding memory cells will not be compared but will be turned off. Thereby, the power consumption is reduced. Further, XOR-based conditional keepers are used to reduce the matching time and the power consumption. Besides, such a circuit is also used to shorten the delay time of the butterfly-type connection.

    摘要翻译： 本发明公开了一种蝴蝶匹配线结构和由此实现的搜索方法，其中增加匹配线的并行性以缩短搜索时间，并且使用蝴蝶型连接来降低功耗并实现最佳能量 效率。 通过蝶型连接，可以在原始独立的并行匹配线之间相互传输信息。 当发生错误情况时，更多的后续存储单元将不被比较，但将被关闭。 从而降低功耗。 此外，基于XOR的条件保持器用于减少匹配时间和功耗。 此外，这种电路也用于缩短蝴蝶式连接的延迟时间。

    XOR-based conditional keeper and an architecture implementing its application to match lines
    28.
    发明授权
    XOR-based conditional keeper and an architecture implementing its application to match lines 有权
    基于XOR的条件守护者和实现其应用程序以匹配行的架构

    公开(公告)号：US07358768B2

    公开(公告)日：2008-04-15

    申请号：US11328110

    申请日：2006-01-10

    申请人： Chung-Hsien Hua ,  Chi-Wei Peng ,  Wei Hwang

    发明人： Chung-Hsien Hua ,  Chi-Wei Peng ,  Wei Hwang

    IPC分类号： G06F7/50 ,  H03K19/21 ,  H03K19/096

    CPC分类号： G11C15/04

    摘要： The present invention discloses an XOR-based conditional keeper and an architecture implementing its application to match lines, wherein the XOR gate in the conditional keeper receives a clock signal synchronous with CAM (Content Addressable Memory) cells and cooperates with a floating signal from the floating node to create an XOR control signal, and the XOR control signal is transmitted to a P-type transistor to create a data signal to control the XOR-based conditional keeper so that the XOR-based conditional keeper can execute an appropriate corresponding action, which can replace the conventional keepers of merely “on” and “off” modes. Further, the XOR-based conditional keeper of the present invention can apply to the dynamic CAM match line architecture so that the dynamic match line can have lower power consumption, higher noise immunity, and high processing speed. Further, the XOR-based conditional keeper of the present invention can also apply to all kinds of dynamic circuits, particularly to a high fan-in circuit.

    摘要翻译： 本发明公开了一种基于XOR的条件跟踪器和实现其应用来匹配线路的架构，其中条件保持器中的异或门接收与CAM（内容可寻址存储器）单元同步的时钟信号，并与浮动信号进行协作 节点以产生XOR控制信号，并且XOR控制信号被发送到P型晶体管以创建数据信号以控制基于XOR的条件保持器，使得基于XOR的条件跟踪器可以执行适当的对应动作，其中 可以替代仅仅是“开”和“关”模式的传统守护者。 此外，本发明的基于XOR的条件跟踪器可以应用于动态CAM匹配线路架构，使得动态匹配线路具有较低的功耗，较高的抗噪声性能和较高的处理速度。 此外，本发明的基于XOR的条件保持器也可以应用于各种动态电路，特别是高风扇电路。

    Comparator eliminating need for one's complement logic for signed numbers
    29.
    发明授权
    Comparator eliminating need for one's complement logic for signed numbers 失效
    比较器消除了对符号数字的补码逻辑的需要

    公开(公告)号：US07284028B2

    公开(公告)日：2007-10-16

    申请号：US10287108

    申请日：2002-11-01

    申请人： Wei Hwang ,  Kun Wu

    发明人： Wei Hwang ,  Kun Wu

    IPC分类号： G06F7/50 ,  G06F7/02

    CPC分类号： G06F7/026

    摘要： An apparatus and method for providing high speed computing power with efficient power consumption in a computing environment comprising a comparator with at least one input feed; a sign selector in electronic communication with the comparator; and result flag generator in electronic communication with both the sign selector and the comparator. The sign selector has input data feeds and an equivalent number of dedicated indicators for identifying signed numbers from unsigned numbers for each of the input data feeds. The result flag generator receives a first resultant feed from the comparator and a second resultant feed from the sign selector. The sign selector can be designed to provide a resultant output. The resultant output is generated after collective operations have been performed on the input feeds and selectively on other feeds such as a sign feed and an Ini feed.

    摘要翻译： 一种用于在包括具有至少一个输入馈送的比较器的计算环境中提供高效率功耗的高速计算能力的装置和方法; 与比较器进行电子通信的符号选择器; 和结果标志发生器与符号选择器和比较器进行电子通信。 符号选择器具有输入数据馈送和等效数量的专用指示符，用于从每个输入数据馈送的无符号数中识别有符号数字。 结果标志发生器从比较器接收第一个合成的馈送，并从该符号选择器接收第二个合成的馈送。 符号选择器可以设计成提供合成输出。 在对输入馈送进行集体操作并选择性地在其他馈送（例如符号馈送和Ini馈送）上产生结果输出。

    Method and system for tuning of components for integrated circuits
    30.
    发明授权
    Method and system for tuning of components for integrated circuits 失效
    用于集成电路组件调谐的方法和系统

    公开(公告)号：US06219822B1

    公开(公告)日：2001-04-17

    申请号：US09129717

    申请日：1998-08-05

    申请人： George D. Gristede ,  Wei Hwang ,  Christophe Robert Tretz

    发明人： George D. Gristede ,  Wei Hwang ,  Christophe Robert Tretz

    IPC分类号： H03K1900

    CPC分类号： G06F17/505

    摘要： A method for automatically tuning object sizes in an integrated circuit includes the steps of providing a circuit having objects disposed therein, inputting equations associated with the objects to provide a relationship between a size of the object and timing information of signals transmitted between the objects, extracting transition times of the signals transmitted between objects by simulating the circuit in operation by evaluating the equations and adjusting the sizes of the objects in the circuit according to the timing information and the transition times until user defined criteria are achieved for the circuit. Systems are also provided to carry out the method.

    摘要翻译： 一种用于在集成电路中自动调谐对象尺寸的方法包括以下步骤：提供具有设置在其中的对象的电路，输入与对象相关联的方程，以提供对象的大小与在对象之间传输的信号的定时信息之间的关系，提取 通过在运行中模拟电路的运算中的信号的转换时间，并根据定时信息和转换时间调整电路中的对象的大小，直到电路达到用户定义的标准。 还提供系统来执行该方法。