公开(公告)号：US20070102766A1

公开(公告)日：2007-05-10

申请号：US11163966

申请日：2005-11-04

申请人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

发明人： Toshiharu Furukawa ,  Mark Hakey ,  Steven Holmes ,  David Horak ,  Charles Koburger ,  William Tonti

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28061 ,  H01L21/28114

摘要： A structure and a method for forming the same. The structure includes (a) a semiconductor layer including a channel region disposed between first and second S/D regions; (b) a gate dielectric region on the channel region; (c) a gate region on the gate dielectric region and electrically insulated from the channel region by the gate dielectric region; (d) a protection umbrella region on the gate region, wherein the protection umbrella region comprises a first dielectric material, and wherein the gate region is completely in a shadow of the protection umbrella region; and (e) a filled contact hole (i) directly above and electrically connected to the second S/D region and (ii) aligned with an edge of the protection umbrella region, wherein the contact hole is physically isolated from the gate region by an inter-level dielectric (ILD) layer which comprises a second dielectric material different from the first dielectric material.

摘要翻译： 一种结构及其形成方法。 该结构包括（a）包括设置在第一和第二S / D区之间的沟道区的半导体层; （b）沟道区上的栅介质区; （c）栅极电介质区域上的栅极区域，并且通过栅极电介质区域与沟道区域电绝缘; （d）栅极区域上的保护伞区域，其中保护伞区域包括第一介电材料，并且其中栅极区域完全处于保护伞区域的阴影中; 和（e）直接在第二S / D区域上方并电连接到第二S / D区域的填充接触孔（i）和（ii）与保护伞区域的边缘对准，其中接触孔通过一个 层间介电层（ILD）层，其包括不同于第一介电材料的第二电介质材料。

公开(公告)号：US20070018280A1

公开(公告)日：2007-01-25

申请号：US11527343

申请日：2006-09-26

申请人： William Motsiff ,  William Tonti ,  Richard Williams

发明人： William Motsiff ,  William Tonti ,  Richard Williams

IPC分类号： H01L29/00 ,  H01L21/326

CPC分类号： H01L23/5252 ,  H01L23/5254 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method for providing an antifuse which is closed by laser energy with an electrostatic assist. Two or more metal segments are formed over a semiconductor structure with an air gap or a porous dielectric between the metal segments. Pulsed laser energy is applied to one or more of the metal segments while a voltage potential is applied between the metal segments to create an electrostatic field. The pulsed laser energy softens the metal segment, and the electrostatic field causes the metal segments to move into contact with each other. The electrostatic field reduces the amount of laser energy which must be applied to the semiconductor structure to close the antifuse.

摘要翻译： 一种用于提供通过静电辅助由激光能量闭合的反熔丝的结构和方法。 在半导体结构之间形成两个或更多个金属段，在金属段之间具有气隙或多孔电介质。 将脉冲激光能量施加到一个或多个金属片段，同时在金属片段之间施加电压电位以产生静电场。 脉冲激光能量软化金属片段，静电场使金属片段彼此接触。 静电场减少必须施加到半导体结构以关闭反熔丝的激光能量的量。

公开(公告)号：US20060289864A1

公开(公告)日：2006-12-28

申请号：US11482688

申请日：2006-07-07

申请人： John Fifield ,  Russell Houghton ,  William Tonti

发明人： John Fifield ,  Russell Houghton ,  William Tonti

IPC分类号： H01L29/04 ,  H01L29/74 ,  H01L29/76 ,  H01L29/00 ,  H01L23/62

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S438/957 ,  H01L2924/00

摘要： A programmable element that has a first diode having an electrode and a first insulator disposed between the substrate and said electrode of said first device, said first insulator having a first value of a given characteristic, and an FET having an electrode and a second insulator disposed between the substrate and said electrode of said second device, said second insulator having a second value of said given characteristic that is different from said first value. The electrodes of the diode and the FET are coupled to one another, and a source of programming energy is coupled to the diode to cause it to permanently decrease in resistivity when programmed. The programmed state of the diode is indicated by a current in the FET, which is read by a sense latch. Thus a small resistance change in the diode translates to a large signal gain/change in the latch. This allows the diode to be programmed at lower voltages.

公开(公告)号：US20060286779A1

公开(公告)日：2006-12-21

申请号：US11155029

申请日：2005-06-16

申请人： Roger Booth ,  Louis Hsu ,  Jack Mandelman ,  William Tonti

发明人： Roger Booth ,  Louis Hsu ,  Jack Mandelman ,  William Tonti

IPC分类号： H01L21/76 ,  H01L21/00

CPC分类号： H01L21/76243

摘要： In an aspect, a method is provided for forming a silicon-on-insulator (SOI) layer. The method includes the steps of (1) providing a silicon substrate; (2) selectively implanting the silicon substrate with oxygen using a low implant energy to form an ultra-thin patterned seed layer; and (3) employing the ultra-thin patterned seed layer to form a patterned SOI layer on the silicon substrate. Numerous other aspects are provided.

摘要翻译： 在一方面，提供了一种用于形成绝缘体上硅（SOI）层的方法。 该方法包括以下步骤：（1）提供硅衬底; （2）使用低注入能量用氧选择性地注入硅衬底以形成超薄图案种子层; 和（3）使用超薄图案种子层在硅衬底上形成图案化SOI层。 提供了许多其他方面。

公开(公告)号：US20060220174A1

公开(公告)日：2006-10-05

申请号：US11440199

申请日：2006-05-24

申请人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

发明人： Jeffrey Brown ,  Robert Gauthier ,  Jed Rankin ,  William Tonti

IPC分类号： H01L29/00

CPC分类号： H01L23/5252 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： Standard photolithography is used to pattern and fabricate a final polysilicon wafer imaged structure which is smaller than normal allowable photo-lithographic minimum dimensions. Three different methods are provided to produce such sub-minimum dimension structures, a first method uses a photolithographic mask with a sub-minimum space between minimum size pattern features of the mask, a second method uses a photolithographic mask with a sub-minimum widthwise jog or offset between minimum size pattern features of the mask, and a third method is a combination of the first and second methods. Each of the three methods can be used with three different embodiments, a first embodiment is a polysilicon E-Fuse with a sub-minimum width polysilicon fuse line, a second embodiment is a work function altered/programmed self-aligned MOSFET E-Fuse with a sub-minimum width fuse line, and a third embodiment is a polysilicon MOSFET E-Fuse with a sub-minimum width fuse line which is programmed with a low trigger voltage snapback.

摘要翻译： 使用标准光刻法来图案化和制造最终的多晶硅晶片成像结构，该结构小于正常允许光刻最小尺寸。 提供了三种不同的方法来产生这样的次最小维度结构，第一种方法使用具有掩模的最小尺寸图案特征之间的亚最小空间的光刻掩模，第二种方法使用光刻掩模与次最小宽度方向点动 或掩模的最小尺寸图案特征之间的偏移，第三种方法是第一和第二方法的组合。 三种方法中的每一种可以与三种不同的实施例一起使用，第一实施例是具有亚最小宽度多晶硅熔丝线的多晶硅E熔丝，第二实施例是工作功能改变/编程的自对准MOSFET E-Fuse，具有 亚最小宽度熔丝线，第三实施例是具有低电平触发电压快速编程的亚最小宽度熔丝线的多晶硅MOSFET E-Fuse。

公开(公告)号：US20060136751A1

公开(公告)日：2006-06-22

申请号：US11016219

申请日：2004-12-17

申请人： Anthony Bonaccio ,  Karl Erickson ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

发明人： Anthony Bonaccio ,  Karl Erickson ,  John Fifield ,  Chandrasekharan Kothandaraman ,  Phil Paone ,  William Tonti

IPC分类号： G06F12/14

CPC分类号： G06F12/1433 ,  G06F21/6245

摘要： Techniques and systems whereby operation of and/or access to particular features of an electronic device may be controlled after the device has left the control of the manufacturer are provided. The operation and/or access may be provided based on values stored in non-volatile storage elements, such as electrically programmable fused (eFUSES).

公开(公告)号：US20050287718A1

公开(公告)日：2005-12-29

申请号：US10710256

申请日：2004-06-29

申请人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

发明人： Zachary Berndlmaier ,  Edward Kiewra ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/00 ,  H01L21/334 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

摘要翻译： 本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物， 具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

公开(公告)号：US20050199907A1

公开(公告)日：2005-09-15

申请号：US10708563

申请日：2004-03-11

申请人： Rama Divakaruni ,  Gregory Freeman ,  Marwan Khater ,  William Tonti

发明人： Rama Divakaruni ,  Gregory Freeman ,  Marwan Khater ,  William Tonti

IPC分类号： H01L21/331 ,  H01L27/06 ,  H01L27/082 ,  H01L29/06 ,  H01L29/737 ,  H01L31/072

CPC分类号： H01L29/66242 ,  H01L27/0623 ,  H01L29/0649 ,  H01L29/7378

摘要： Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap and a vacuum void.

摘要翻译： 提供了用于制造双极晶体管的结构和方法，双极晶体管包括集电极，覆盖集电极的本征基极，覆盖本征基极的发射极以及与发射极间隔开的非本征基极，该间隙至少包括 一个气隙和一个真空空隙。

公开(公告)号：US20050186744A1

公开(公告)日：2005-08-25

申请号：US10785895

申请日：2004-02-24

申请人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier, ,  Carl Radens ,  William Tonti

发明人： Wagdi Abadeer ,  Jeffrey Brown ,  Kiran Chatty ,  Robert Gauthier, ,  Carl Radens ,  William Tonti

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/425 ,  H01L21/8234 ,  H01L29/423

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66553 ,  H01L29/6659

摘要： An inverse-T transistor is formed by a method that decouples the halo implant, the deep S/D implant and the extension implant, so that the threshold voltage can be set by adjusting the halo implant without being affected by changes to the extension implant that are intended to alter the series resistance of the device. Formation of the inverse-T structure can be made by a damascene method in which a temporary layer deposited over the layer that will form the cross bar of the T has an aperture formed in it to hold the gate electrode, the aperture being lined with vertical sidewalls that provide space for the ledges that form the T. Another method of gate electrode formation starts with a layer of poly, forms a block for the gate electrode, covers the horizontal surfaces outside the gate with an etch-resistant material and etches horizontally to remove material above the cross bars on the T, the cross bars being protected by the etch resistant material.

摘要翻译： 反向T晶体管通过使晕轮注入，深S / D注入和延伸注入分离的方法形成，使得阈值电压可以通过调整晕轮植入来设定，而不受扩展植入物的变化的影响 旨在改变装置的串联电阻。 逆T结构的形成可以通过镶嵌方法来形成，其中沉积在层上的临时层将形成T的横杆，其中形成有形成在其中的孔以保持栅电极，孔径垂直排列 为形成T的壁架提供空间的侧壁。栅电极形成的另一种方法从多层开始，形成用于栅电极的块，用耐蚀刻材料覆盖栅极外的水平表面，并水平蚀刻 去除T上的横杆上方的材料，横杆由耐蚀刻材料保护。

公开(公告)号：US20050073023A1

公开(公告)日：2005-04-07

申请号：US10605523

申请日：2003-10-06

申请人： John Fifield ,  Wagdi Abadeer ,  William Tonti

发明人： John Fifield ,  Wagdi Abadeer ,  William Tonti

IPC分类号： H01L23/525 ,  H01L21/82 ,  H01L29/00

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An antifuse device (120) that includes a bias element (124) and an programmable antifuse element (128) arranged in series with one another so as to form a voltage divider having an output node (F) located between the bias and antifuse elements. When the antifuse device is in its unprogrammed state, each of the bias element and antifuse element is non-conductive. When the antifuse device is in its programmed state, the bias element remains non-conductive, but the antifuse element is conductive. The difference in the resistance of the antifuse element between its unprogrammed state and programmed state causes the difference in voltages seen at the output node to be on the order of hundreds of mili-volts when a voltage of 1 V is applied across the antifuse device. This voltage difference is so high that it can be readily sensed using a simple sensing circuit (228).

摘要翻译： 一种反熔丝装置（120），其包括彼此串联布置的偏置元件（124）和可编程反熔丝元件（128），以形成具有位于偏置和反熔丝元件之间的输出节点（F）的分压器。 当反熔丝装置处于其未编程状态时，偏置元件和反熔丝元件中的每一个都是不导电的。 当反熔丝装置处于其编程状态时，偏置元件保持不导电，但是反熔丝元件是导电的。 反熔丝元件在其未编程状态和编程状态之间的电阻差异导致当在反熔断器件上施加1V的电压时，在输出节点处看到的电压差为几百微升。 该电压差非常高以至于可以使用简单的感测电路（228）容易地感测。