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21.发明授权Method and system to indicate an exception-triggering page within a microprocessor 有权用于指示微处理器内的异常触发页面的方法和系统公开(公告)号：US07689806B2
公开(公告)日：2010-03-30
申请号：US11487284
申请日：2006-07-14
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/684
摘要： A method and system to indicate which page within a software-managed page table triggers an exception within a microprocessor, such as, for example, a digital signal processor, wherein a software-managed translation lookaside buffer (TLB) module receives a virtual address produced by an instruction within a Very Long Instruction Word (VLIW) packet, such as, for example, a fetch instruction, and further compares the virtual address to each stored TLB entry. If a match exists, then the TLB module outputs a corresponding mapped physical address for the instruction. Otherwise, if the VLIW packet spans two pages, where a first page is present as a TLB entry within the TLB module and the second page is missing from the stored TLB entries, an indication bit within a data field of a control register is set to identify the TLB miss exception to a software management unit. The software management unit retrieves the indication bit information from the register and further performs a page table look-up within the software-managed page table using the indication bit information in order to retrieve the missing page information. Subsequently, the missing page information is written into a new TLB entry within the TLB module for subsequent virtual address translation and execution of the packet of instructions.
摘要翻译： 一种方法和系统，用于指示软件管理的页表内的哪个页面在微处理器（例如数字信号处理器）内触发异常，其中软件管理的翻译后备缓冲器（TLB）模块接收产生的虚拟地址 通过超长指令字（VLIW）分组（例如，取指令）中的指令，并且还将虚拟地址与每个存储的TLB条目进行比较。 如果匹配存在，则TLB模块输出相应的映射物理地址。 否则，如果VLIW分组跨越两页，其中第一页作为TLB模块中的TLB条目存在，并且第二页从存储的TLB条目丢失，则将控制寄存器的数据字段内的指示位设置为 识别软件管理单元的TLB错误异常。 软件管理单元从寄存器检索指示位信息，并使用指示位信息进一步在软件管理的页表中执行页表查找，以便检索丢失页信息。 随后，丢失的页面信息被写入TLB模块中的新TLB条目，用于随后的虚拟地址转换和指令分组的执行。
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22.发明授权Processor and method of grouping and executing dependent instructions in a packet 有权分组和执行分组中的相关指令的处理器和方法公开(公告)号：US07523295B2
公开(公告)日：2009-04-21
申请号：US11086475
申请日：2005-03-21
CPC分类号： G06F9/3885 , G06F9/3851 , G06F9/3853
摘要： An interleaved multithreading pipeline operating method comprises reading an instruction packet containing at least two instructions, steering a first instruction of the instruction packet to a first execution unit for execution and generating a first result, steering a second instruction of the instruction packet to a second execution unit for execution using the first result and generating a second result, and storing the second result.
摘要翻译： 交错多线程流水线操作方法包括读取包含至少两个指令的指令分组，将指令分组的第一指令转向第一执行单元以执行并产生第一结果，将指令分组的第二指令转向第二执行 使用第一结果执行的单元并产生第二结果，并存储第二结果。
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公开(公告)号：US20070266229A1
公开(公告)日：2007-11-15
申请号：US11431732
申请日：2006-05-10
申请人： Erich Plondke , Robert Lester , Lucian Codrescu , Muhammad Ahmed
发明人： Erich Plondke , Robert Lester , Lucian Codrescu , Muhammad Ahmed
IPC分类号： G06F9/44
CPC分类号： G06F9/30149 , G06F9/325 , G06F9/3853 , G06F9/3885
摘要： Methods and apparatus for encoding information regarding a hardware loop of a set of packets is provided, each packet (400) containing instructions. The information is encoded into one or more bits of at least one instruction (300) in the set of packets. The information may indicate whether a packet is or is not an end packet of the loop. Information regarding two hardware loops may be encoded where information regarding the first loop is encoded into an instruction at a first position in each packet and information regarding the second loop is encoded into an instruction at a second position in each packet. End instruction information may be encoded into an instruction not having encoded loop information at the same bit positions reserved for the encoded loop information, the end instruction information indicating whether an instruction is the last instruction of a packet and the length of a packet.
摘要翻译： 提供了用于编码关于一组分组的硬件循环的信息的方法和装置，每个分组（400）包含指令。 信息被编码成该组分组中的至少一个指令（300）的一个或多个位。 信息可以指示分组是否是循环的结束分组。 关于两个硬件循环的信息可以被编码，其中关于第一循环的信息被编码为每个分组中的第一位置处的指令，并且关于第二循环的信息被编码为每个分组中的第二位置处的指令。 结束指令信息可以被编码为在编码环路信息保留的相同位位置处不具有编码环路信息的指令，表示指令是分组的最后指令还是分组长度的结束指令信息。
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24.发明授权System and method of executing program threads in a multi-threaded processor 有权在多线程处理器中执行程序线程的系统和方法公开(公告)号：US07814487B2
公开(公告)日：2010-10-12
申请号：US11115917
申请日：2005-04-26
CPC分类号： G06F9/3851 , G06F9/3853
摘要： A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.
摘要翻译： 公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。 第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。 这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。 此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。 当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。
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25.发明授权Method and system for encoding variable length packets with variable instruction sizes 有权用可变指令大小编码可变长度数据包的方法和系统公开(公告)号：US07526633B2
公开(公告)日：2009-04-28
申请号：US11088607
申请日：2005-03-23
CPC分类号： G06F9/30149 , G06F9/3853
摘要： Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.
摘要翻译： 用于在通信（例如，CDMA）系统中处理传输的技术。 该方法和系统编码和处理混合长度（例如，16位和32位）的指令以及包括混合长度指令的指令包。 这包括编码第一长度的多个指令和第二长度的多个指令。 该方法和系统对具有至少一个指令长度位的报头进行编码。 指令位区分第一长度的指令和第二长度的指令，以使相关的DSP在混合流中进行处理。 方法和系统根据指令长度位的内容区分第一长度的指令和第二长度的指令。 标题还包括用于区分指令包中不同长度的指令的位。
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公开(公告)号：US07383420B2
公开(公告)日：2008-06-03
申请号：US11089619
申请日：2005-03-24
CPC分类号： G06F9/35 , G06F9/3851 , G06F9/3853
摘要： A processor is operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the first register-out value and obtaining a second register-out value, and storing the second register-out value into a third register based on the program instruction. The processor is further operable to carry out a method that comprises accessing a first register based on a program instruction and obtaining a first register-out value, accessing a second register based on the program instruction and obtaining a second register-out value, and storing the first register-out value into a third register based on the second register-out value.
摘要翻译： 处理器可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于第一寄存器输出值访问第二寄存器并获得第二寄存器值， 以及基于所述程序指令将所述第二寄存器值存储到第三寄存器中。 处理器还可操作以执行一种方法，该方法包括基于程序指令访问第一寄存器并获得第一寄存器值，基于所述程序指令访问第二寄存器并获得第二寄存器值，以及存储 基于第二寄存器值将第一寄存器值输入到第三寄存器中。
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公开(公告)号：US20060294341A1
公开(公告)日：2006-12-28
申请号：US11165757
申请日：2005-06-23
申请人： Erich Plondke , William Anderson , Lucian Codrescu
发明人： Erich Plondke , William Anderson , Lucian Codrescu
IPC分类号： G06F12/00
CPC分类号： G06F9/4812 , G06F12/1027 , Y02D10/13 , Y02D10/24
摘要： A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
摘要翻译： 共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新启用异常和可选中断，解决原因 异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。
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28.发明授权公开(公告)号：US07676647B2
公开(公告)日：2010-03-09
申请号：US11506584
申请日：2006-08-18
申请人： Lucian Codrescu , Erich Plondke , Taylor Simpson
发明人： Lucian Codrescu , Erich Plondke , Taylor Simpson
IPC分类号： G06F15/00
CPC分类号： G06F9/30101 , G06F9/30021 , G06F9/30094 , G06F9/3885
摘要： A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.
摘要翻译： 公开了一种处理器装置，其包括具有用于标量和矢量操作的组合条件码寄存器的寄存器文件。 处理器设备利用组合条件码寄存器进行标量和矢量操作。 此外，比较操作可以将结果位存储在组合条件码寄存器中，并且条件操作可以利用组合条件码寄存器位来评估条件。
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29.发明申请Method and system to combine multiple register units within a microprocessor 有权在微处理器内组合多个寄存器单元的方法和系统公开(公告)号：US20080184007A1
公开(公告)日：2008-07-31
申请号：US11498627
申请日：2006-08-02
申请人： Lucian Codrescu , Erich Plondke , Mao Zeng
发明人： Lucian Codrescu , Erich Plondke , Mao Zeng
CPC分类号： G06F9/30032 , G06F9/30036 , G06F9/30112
摘要： A method and system to combine multiple register units within a microprocessor, such as, for example, a digital signal processor, are described. A first register unit and a second register unit are retrieved from a register file structure within a processing unit, the first register unit and the second register unit being non-adjacently located within the register file structure. The first register unit and the second register unit are further combined during execution of a single instruction to form a resulting register unit. Finally, the resulting register unit is stored within the register file structure for further processing. Alternatively, a first half word unit from the first register unit and a second half word unit from the second register unit are retrieved. The first half word unit and the second half word unit are further input into corresponding high and low portions of a resulting register unit to form the resulting register unit during execution of a single instruction. Finally, the resulting register unit is stored within the register file structure for further processing.
摘要翻译： 描述了在微处理器内组合多个寄存器单元的方法和系统，例如数字信号处理器。 从处理单元内的寄存器文件结构检索第一寄存器单元和第二寄存器单元，第一寄存器单元和第二寄存器单元非相邻地位于寄存器堆栈结构内。 在执行单个指令期间，第一寄存器单元和第二寄存器单元进一步组合以形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。 或者，检索来自第一寄存器单元的第一半字单元和来自第二寄存器单元的第二半字单元。 第一半字单元和第二半字单元进一步输入到所得寄存器单元的对应高和低部分，以在单个指令的执行期间形成结果寄存器单元。 最后，所得到的寄存器单元被存储在寄存器堆栈结构中用于进一步处理。
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公开(公告)号：US07398371B2
公开(公告)日：2008-07-08
申请号：US11165757
申请日：2005-06-23
CPC分类号： G06F9/4812 , G06F12/1027 , Y02D10/13 , Y02D10/24
摘要： A shared translation look-aside buffer method comprises saving data stored in a first selected set of registers to a predetermined section of a thread-specific area in memory upon encountering an exception/interrupt, re-enabling exceptions and optionally interrupts, addressing a cause of the exception/interrupt while safely permitting another exception, and restoring the saved data to the first selected set of registers.
摘要翻译： 共享翻译后备缓冲方法包括：当遇到异常/中断时，将存储在第一选定寄存器组中的数据保存到存储器中线程特定区域的预定部分，重新启用异常和可选中断，解决原因 异常/中断，同时安全地允许另一个异常，并将保存的数据恢复到第一选定的寄存器组。
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