公开(公告)号：US20220068387A1

公开(公告)日：2022-03-03

申请号：US17011039

申请日：2020-09-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Kai HSU ,  Teng-Hao YEH

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G06F7/544 ,  G06N5/04

Abstract: An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched.

公开(公告)号：US20210335804A1

公开(公告)日：2021-10-28

申请号：US16857226

申请日：2020-04-24

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao YEH ,  Hang-Ting LUE ,  Chih-Wei HU

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

Abstract: A semiconductor structure and a method for manufacturing the same. The semiconductor structure includes a first staircase structure, a second staircase structure, a conductive pillar, and a contact pillar. The first staircase structure includes conductive stair layers. The conductive pillar passes through the second staircase structure. The conductive pillar has an upper conductive pillar end and a lower conductive pillar end opposing to the upper conductive pillar end. The contact pillar is electrically connected on one conductive stair layer of the conductive stair layers. The contact pillar has an upper contact end and a lower contact end opposing to the upper contact end. The upper contact end and the lower contact end are respectively electrically connected to the upper conductive pillar end of the conductive pillar and the one conductive stair layer.

公开(公告)号：US20200258898A1

公开(公告)日：2020-08-13

申请号：US16273301

申请日：2019-02-12

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei HU ,  Teng-Hao YEH ,  Yu-Wei JIANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/28 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528

Abstract: A three-dimensional memory device includes a substrate, conductive layers and insulating layers, a storage layer, a first channel, a second channel and a first conductive plug. The conductive layers and insulating layers are alternately stacked over the substrate to form a multi-layer stacked structure. The storage layer penetrates through the multi-layer stacked structure, and has a first string portion and a second string portion that are spaced from each other. The first channel is located on a lateral side of the first string portion. The second channel is located on a lateral side of the second string portion. The first channel and the second channel have an upper channel portion and a lower channel portion. The first conductive plug is interconnected between the upper channel portion and the lower channel portion.

公开(公告)号：US20170018570A1

公开(公告)日：2017-01-19

申请号：US15279203

申请日：2016-09-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Hang-Ting LUE ,  Teng-Hao YEH

IPC: H01L27/115 ,  H01L27/02 ,  H01L49/02 ,  H01L27/06

CPC classification number: H01L28/90 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/11526 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L28/60

Abstract: An integrated circuit includes a 3D NAND memory array with a stack of conductive strips and a capacitor with a stack of capacitor terminal strips. Multiple conductive strips in the stack of conductive strips, and multiple capacitor terminal strips of the stack of capacitor terminal strips, share a same plurality of plane positions relative to the substrate. Different plane positions in the same plurality of plane positions characterize different capacitor terminal strips in the stack of capacitor terminal strips and different conductive strips in the stack of conductive strips, and a same plane position characterizing both a conductive strip in the stack of conductive strips and a capacitor terminal strip in the stack of capacitor terminal strips indicates that the conductive strip and the capacitor terminal strip have a same vertical position relative to each other.

Abstract translation: 集成电路包括具有导电条的堆叠的3D NAND存储器阵列和具有堆叠的电容器端子条的电容器。 导电带堆叠中的多个导电条和电容器端子条的堆叠的多个电容器端子条相对于基板共享相同的多个平面位置。 在相同多个平面位置中的不同平面位置表示电容器端子条的堆叠中的不同的电容器端子条和导电条的堆叠中的不同的导电条，以及表征导电条的堆叠中的导电条的同一平面位置 电容器端子排堆叠中的电容器端子条表示导电条和电容器端子条相对于彼此具有相同的垂直位置。

公开(公告)号：US20160086971A1

公开(公告)日：2016-03-24

申请号：US14948482

申请日：2015-11-23

Applicant: Macronix International Co., Ltd

Inventor： Teng-Hao YEH ,  Chih-Wei HU ,  Yen-Hao SHIH

IPC: H01L27/115 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/28282 ,  H01L27/11565 ,  H01L29/511 ,  H01L29/518

Abstract: A memory array includes a plurality of ridge-shaped multi-layer stacks extending along a first direction, and a hard mask layer formed on top of the plurality of ridge-shaped multi-layer stacks. The hard mask layer includes a plurality of stripes vertically aligned with the plurality of ridge-shaped multi-layer stacks, respectively, a plurality of bridges connecting adjacent ones of the stripes along a second direction orthogonal to the first direction, and a plurality of hard mask through holes between the plurality of bridges and the plurality of stripes.