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    Linear amplifier having higher efficiency for envelope tracking modulator
    21.
    发明授权
    Linear amplifier having higher efficiency for envelope tracking modulator 有权

    公开(公告)号：US10608592B2

    公开(公告)日：2020-03-31

    申请号：US15871045

    申请日：2018-01-14

    Applicant: MEDIATEK INC.

    Inventor： Chen-Yen Ho ,  Yu-Hsin Lin

    IPC: H03F3/45 ,  H03F1/02 ,  H03F1/22 ,  H03F1/48 ,  H03F3/30

    Abstract: A linear amplifier is provided to have higher efficiency for an envelope tracking modulator. In one embodiment, a first stage amplifier circuit can be simply operated in a high gain mode or a high bandwidth mode for different applications, without using large chip area. In another embodiment, an output stage has a cascode structure whose dynamic range is controlled according to a voltage level of a supply voltage, to make a core device within the output stage have better protection and suitable dynamic range.

    Filters with order enhancement
    25.
    发明授权
    Filters with order enhancement 有权
    具有订单增强功能的过滤器

    公开(公告)号：US08810308B2

    公开(公告)日：2014-08-19

    申请号：US13758028

    申请日：2013-02-04

    Applicant: MediaTek Inc.

    Inventor： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Chi-Lun Lo ,  Chen-Yen Ho

    IPC: H03K5/00 ,  H03H11/12

    CPC classification number: H03H11/1204 ,  H03H11/1252 ,  H03H11/126

    Abstract: A filter is provided. The filter receives an input signal and generates an output signal according to the input signal. The filter includes an input network, a high-pass network, and an operational circuit. The first input network provides a first normal path for the input signal to generate a first normal signal. The first high-pass network provides a first high-pass path for the input signal to generate a first high-pass signal. The operational circuit has first and second input terminals. The polarity of the second input terminal is inverse to that of the first input terminal. The operational circuit receives the first normal signal by the first input terminal and the first high-pass signal by the second input terminal such that a subtraction operation is performed on the first normal signal and the first high-pass filter to accomplish a low-pass filtering operation for generating the output signal.

    Abstract translation: 提供了一个过滤器。 滤波器接收输入信号，并根据输入信号产生输出信号。 滤波器包括输入网络，高通网络和操作电路。 第一输入网络为输入信号提供第一正常路径以产生第一正常信号。 第一高通网络为输入信号提供第一高通路径以产生第一高通信号。 该操作电路具有第一和第二输入端。 第二输入端子的极性与第一输入端子的极性相反。 操作电路由第一输入端接收第一正常信号和由第二输入端接收第一高通信号，使得对第一正常信号和第一高通滤波器执行减法运算以完成低通 用于产生输出信号的滤波操作。

    SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER AND RELATED SIGMA-DELTA MODULATION METHOD
    26.
    发明申请
    SIGMA-DELTA MODULATOR WITH SAR ADC AND TRUNCATER AND RELATED SIGMA-DELTA MODULATION METHOD 有权
    具有SAR ADC和TRANCATER的SIGMA-DELTA调制器及相关SIGMA-DELTA调制方法

    公开(公告)号：US20130088376A1

    公开(公告)日：2013-04-11

    申请号：US13691860

    申请日：2012-12-03

    Applicant: Mediatek Inc.

    Inventor： Yu-Hsin Lin ,  Hung-Chieh Tsai ,  Sheng-Jui Huang

    IPC: H03M3/00

    CPC classification number: H03M3/30 ,  H03M3/412 ,  H03M3/426 ,  H03M7/3042

    Abstract: A sigma-delta modulator includes a processing circuit, a quantizer, a truncater and a feedback circuit. The processing circuit receives an input signal and an analog information and generates an integrated signal by perform an integration upon a difference between the input signal and the analog information. The quantizer includes a successive approximation register (SAR) analog-to-digital converter (ADC) for receiving the integrated signal and generating a digital information according to the integrated signal. The truncater receives the digital information and generates a truncated information according to the digital information. The feedback circuit generates the analog information to the processing circuit according to the truncated information.

    Abstract translation: Σ-Δ调制器包括处理电路，量化器，截短器和反馈电路。 处理电路接收输入信号和模拟信息，并通过根据输入信号和模拟信息之间的差进行积分来产生积分信号。 量化器包括用于接收积分信号并根据积分信号产生数字信息的逐次逼近寄存器（SAR）模拟 - 数字转换器（ADC）。 截断器接收数字信息并根据数字信息产生截断的信息。 反馈电路根据截断的信息向处理电路生成模拟信息。

    Fast-transient buffer
    28.
    发明授权
    Fast-transient buffer 有权

    公开(公告)号：US12224739B2

    公开(公告)日：2025-02-11

    申请号：US18299852

    申请日：2023-04-13

    Applicant: MEDIATEK INC.

    Inventor： Yueh-Min Chen ,  Ting-Yang Wang ,  Yu-Hsin Lin ,  Wen-Chieh Wang

    IPC: H03K17/16 ,  H03K17/06 ,  H03K17/687

    Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.

    Low power quadrature phase detector
    29.
    发明授权
    Low power quadrature phase detector 有权

    公开(公告)号：US12212325B2

    公开(公告)日：2025-01-28

    申请号：US17857161

    申请日：2022-07-04

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03L7/087 ,  H03K17/687 ,  H03L7/07 ,  H03L7/107

    Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

    5G REGISTRATION RESULTANT VALUE HANDLING
    30.
    发明公开
    5G REGISTRATION RESULTANT VALUE HANDLING 审中-公开

    公开(公告)号：US20240040530A1

    公开(公告)日：2024-02-01

    申请号：US18218097

    申请日：2023-07-04

    Applicant: MEDIATEK INC.

    Inventor： Yu-Hsin Lin ,  Yung-Chun Yang ,  Yuan-Chieh Lin

    IPC: H04W60/00

    CPC classification number: H04W60/005

    Abstract: A method of determining UE registration status for a UE that is registered to different PLMN networks over 3GPP and non-3GPP accesses is proposed. The UE triggers registration to a second Public Land Mobile Network (PLMN) or Standalone Non-Public Network (SNPN) over a second access, and receives a REGISTRATION ACCEPT message from the second network over the second access. The REGISTRATION ACCEPT message carries a 5GS registration result IE having a 5GS registration result value. If the 5GS registration result value indicates that the UE is registered (or not registered) to a first network over a first access, then the UE may ignore the indication and considers the UE is not registered (or registered) to the first network over the first access.

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