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    LOW POWER QUADRATURE PHASE DETECTOR
    1.
    发明申请
    LOW POWER QUADRATURE PHASE DETECTOR 有权

    公开(公告)号：US20230113143A1

    公开(公告)日：2023-04-13

    申请号：US17857161

    申请日：2022-07-04

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03L7/087 ,  H03L7/107 ,  H03L7/07 ,  H03K17/687

    Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

    FILTER CIRCUIT USING POLYPHASE FILTER WITH DYNAMIC RANGE ENHANCEMENT
    2.
    发明申请
    FILTER CIRCUIT USING POLYPHASE FILTER WITH DYNAMIC RANGE ENHANCEMENT 有权

    公开(公告)号：US20220182040A1

    公开(公告)日：2022-06-09

    申请号：US17503385

    申请日：2021-10-18

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03H11/04

    Abstract: A filter circuit includes a polyphase filter used to generate a plurality of output signals with different phases according to a plurality of input signals. The polyphase filter includes a switch circuit and a feed-forward capacitor. The switch circuit has a control terminal used to receive a control voltage, a first connection terminal used to output one of the output signals, and a second connection terminal used to receive one of the input signals. The feed-forward capacitor has a first plate coupled to the second connection terminal of the switch circuit and a second plate coupled to the control terminal of the switch circuit.

    Poly phase filter with phase error enhance technique
    4.
    发明授权
    Poly phase filter with phase error enhance technique 有权

    公开(公告)号：US11811413B2

    公开(公告)日：2023-11-07

    申请号：US17864416

    申请日：2022-07-14

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03K5/135 ,  H03K5/14 ,  H03L7/085

    CPC classification number: H03K5/135 ,  H03K5/14 ,  H03L7/085

    Abstract: The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

    POLY PHASE FILTER WITH PHASE ERROR ENHANCE TECHNIQUE
    5.
    发明申请
    POLY PHASE FILTER WITH PHASE ERROR ENHANCE TECHNIQUE 有权

    公开(公告)号：US20230114343A1

    公开(公告)日：2023-04-13

    申请号：US17864416

    申请日：2022-07-14

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03K5/135 ,  H03K5/14 ,  H03L7/085

    Abstract: The present invention provides a filtering circuit comprising a poly phase filter and a quadrature phase detector. The poly phase filter comprises a first path, a second path, a third path and a fourth path. The first path is configured to receive a first input signal to generate a first clock signal. The second path comprising a first adjustable delay circuit is configured to receive the first input signal to generate a second clock signal. The third path comprising a second adjustable delay circuit is configured to receive a second input signal to generate a third clock signal. The fourth path is configured to receive the second input signal to generate a fourth clock signal. The quadrature phase detector is configured to detect phases of these clock signals to generate control signals to control the first adjustable delay circuit and the second adjustable delay circuit.

    Fast-transient buffer
    9.
    发明授权
    Fast-transient buffer 有权

    公开(公告)号：US12224739B2

    公开(公告)日：2025-02-11

    申请号：US18299852

    申请日：2023-04-13

    Applicant: MEDIATEK INC.

    Inventor： Yueh-Min Chen ,  Ting-Yang Wang ,  Yu-Hsin Lin ,  Wen-Chieh Wang

    IPC: H03K17/16 ,  H03K17/06 ,  H03K17/687

    Abstract: A fast-transient buffer is shown. The fast-transient buffer has a flipped voltage follower coupled between the input terminal and the output terminal of the fast-transient buffer, and a first MOS transistor coupled to the flipped voltage follower as well as the output terminal of the fast-transient buffer. The first MOS transistor regulates the output voltage of the output terminal of the fast-transient buffer, in the opposite direction in comparison with an output voltage regulation direction due to the flipped voltage follower.

    Low power quadrature phase detector
    10.
    发明授权
    Low power quadrature phase detector 有权

    公开(公告)号：US12212325B2

    公开(公告)日：2025-01-28

    申请号：US17857161

    申请日：2022-07-04

    Applicant: MEDIATEK INC.

    Inventor： Fong-Wen Lee ,  Wen-Chieh Wang ,  Yu-Hsin Lin

    IPC: H03L7/087 ,  H03K17/687 ,  H03L7/07 ,  H03L7/107

    Abstract: The present invention provides a quadrature phase detector including a detection circuit. The detection circuit includes a first switch, a second switch and a first filter, wherein the first switch is controlled by a second clock signal to selectively couple a first clock signal to a first node, the second switch is controlled by the second clock signal to selectively coupled the first node to a reference voltage, and the first filter is configured to filter voltages at the first node to generate a first detection result.

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