公开(公告)号：US20210176345A1

公开(公告)日：2021-06-10

申请号：US16708470

申请日：2019-12-10

Applicant: Mellanox Technologies, Ltd.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L29/06 ,  G06F9/455 ,  H04L29/08 ,  H04L12/46 ,  H04L12/24

Abstract: One embodiment includes a network device, including hardware parsers to receive data of a header section of a packet, the header section including respective headers, parser configuration registers to store a default parsing configuration data set, wherein at least one of the hardware parsers is configured to parse at least one of the headers responsively to the default parsing configuration data set, yielding first parsed data, a packet processing engine to select a selected parsing configuration data set from a selection of parsing configuration data sets responsively to the first parsed data, cause loading of the selected parsing configuration data set into the parser configuration registers, and wherein ones of the hardware parsers are configured to parse respective ones of the headers responsively to the selected parsing configuration data set, yielding second parsed data, and process the packet responsively to the second parsed data.

公开(公告)号：US10454991B2

公开(公告)日：2019-10-22

申请号：US14658260

申请日：2015-03-16

Applicant: Mellanox Technologies Ltd.

Inventor： Noam Bloch ,  Ariel Shachar ,  Michael Kagan ,  Lior Narkis ,  Shlomo Raikin

IPC: H04L29/08 ,  G06F9/455

Abstract: A network interface device includes a host interface for connection to a host processor and a network interface, which is configured to transmit and receive data packets over a network, and which comprises multiple distinct physical ports configured for connection to the network. Processing circuitry is configured to receive, via one of the physical ports, a data packet from the network and to decide, responsively to a destination identifier in the packet, whether to deliver a payload of the data packet to the host processor via the host interface or to forward the data packet to the network via another one of the physical ports.

公开(公告)号：US20190253362A1

公开(公告)日：2019-08-15

申请号：US15896128

申请日：2018-02-14

Applicant: Mellanox Technologies, Ltd.

Inventor： Jacob Ruthstein ,  David Mozes ,  Dror Bohrer ,  Ariel Shahar ,  Lior Narkis ,  Noam Bloch

IPC: H04L12/851 ,  H04L12/801 ,  H04L12/26

Abstract: Packet flows received in a data network are assigned to respective entries of a database. During an accumulation interval byte counts of the assigned packet flows are accumulated in the respective database entries. The packet flows are classified as elephant flows when differences between the byte counts and a reference byte count exceed a threshold and are reported after expiration of the accumulation interval.

公开(公告)号：US10027601B2

公开(公告)日：2018-07-17

申请号：US14729127

申请日：2015-06-03

Applicant: Mellanox Technologies Ltd.

Inventor： Lior Narkis ,  Noam Bloch

IPC: H04L12/935 ,  H04L29/06 ,  H04L12/70

Abstract: Communication apparatus includes a host interface, which is configured to be connected to a peripheral component bus, and a network interface, which is configured to be connected to a network. Packet processing circuitry is coupled between the host interface and the network interface and is configured to receive from a first interface, selected from among the host interface and the network interface, a data packet comprising a header containing multiple fields having respective values, to identify, responsively to a value of at least one of the fields, a corresponding entry in a header modification table, and to modify the header in accordance with the identified entry. The data packet with the modified header is transmitted through a second interface selected from among the host interface and the network interface.

公开(公告)号：US20160359768A1

公开(公告)日：2016-12-08

申请号：US14729127

申请日：2015-06-03

Applicant: Mellanox Technologies Ltd.

Inventor： Lior Narkis ,  Noam Bloch

IPC: H04L12/935 ,  H04L29/06

CPC classification number: H04L49/3009 ,  H04L69/22 ,  H04L2012/5652

Abstract: Communication apparatus includes a host interface, which is configured to be connected to a peripheral component bus, and a network interface, which is configured to be connected to a network. Packet processing circuitry is coupled between the host interface and the network interface and is configured to receive from a first interface, selected from among the host interface and the network interface, a data packet comprising a header containing multiple fields having respective values, to identify, responsively to a value of at least one of the fields, a corresponding entry in a header modification table, and to modify the header in accordance with the identified entry. The data packet with the modified header is transmitted through a second interface selected from among the host interface and the network interface.

Abstract translation: 通信设备包括被配置为连接到外围组件总线的主机接口和被配置为连接到网络的网络接口。 分组处理电路耦合在主机接口和网络接口之间，并且被配置为从主机接口和网络接口中选择的第一接口接收包括包含具有相应值的多个字段的报头的数据分组， 响应于字段中的至少一个的值，标题修改表中的相应条目，并且根据所识别的条目修改标题。 具有修改的报头的数据分组通过从主机接口和网络接口中选择的第二接口传输。

公开(公告)号：US20250028658A1

公开(公告)日：2025-01-23

申请号：US18224262

申请日：2023-07-20

Applicant: Mellanox Technologies, Ltd.

Inventor： Ortal Ben Moshe ,  Roee Moyal ,  Shay Aisman ,  Gil Bloch ,  Ariel Shahar ,  Roman Nudelman ,  Gil Kremer ,  Yossef Itigin ,  Lior Narkis

IPC: G06F13/16 ,  G06F9/54

Abstract: Systems and methods are described herein for processing data packets. An example network adapter may include a network interface operatively coupled to a communication network and a packet processing circuitry operatively coupled to the network interface. The packet processing circuitry may receive, via the network interface, a message; retrieve, via a packet processing circuitry, a work queue element (WQE) index identifying a position of a WQE in a receive queue; determine that the message is associated with a small payload; process the message without consuming the WQE; receive, via the network interface, a subsequent message; and process the subsequent message using the WQE. In this way, the systems and methods describe herein reduce the latency in processing of the data packets.

公开(公告)号：US20220377014A1

公开(公告)日：2022-11-24

申请号：US17874352

申请日：2022-07-27

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Avi Urman ,  Lior Narkis ,  Noam Bloch

IPC: H04L45/745 ,  H04L69/22 ,  G06F13/42

Abstract: A communication apparatus includes a host interface, connected to a peripheral component bus so as to communicate with a CPU and a memory of a host computer. A network interface is connected to a network. Packet processing circuitry is configured to receive from a first interface a data packet including a set of one or more headers that include header fields having respective values, to identify, responsively to at least one of the header fields, a corresponding entry in a header modification table that specifies a header modification operation, to modify the set of headers in accordance with the header modification operation, to check whether the entry specifies an additional header modification operation, to output the modified set of headers if the entry does not specify an additional header modification operation, and, if the entry specifies an additional header modification operation, to feed-back the modified set of headers.

公开(公告)号：US11476928B2

公开(公告)日：2022-10-18

申请号：US16921993

申请日：2020-07-07

Applicant: Mellanox Technologies, Ltd.

Inventor： Dotan David Levi ,  Avi Urman ,  Lior Narkis ,  Liron Mula ,  Paraskevas Bakopoulos ,  Ariel Almog ,  Roee Moyal ,  Gal Yefet

IPC: H04B7/26 ,  H04L49/351 ,  H04L49/90 ,  H04W72/04 ,  H04W74/08

Abstract: A network element one or more network ports, network time circuitry and packet processing circuitry. The network ports are configured to communicate with a communication network. The network time circuitry is configured to track a network time defined in the communication network. In some embodiments the packet processing circuitry is configured to receive a definition of one or more timeslots that are synchronized to the network time, and to send outbound packets to the communication network depending on the timeslots. In some embodiments the packet processing circuitry is configured to process inbound packets, which are received from the communication network, depending on the timeslots.

公开(公告)号：US20220283964A1

公开(公告)日：2022-09-08

申请号：US17189303

申请日：2021-03-02

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Idan Burstein ,  Dotan David Levi ,  Ariel Shahar ,  Lior Narkis ,  Igor Voks ,  Noam Bloch ,  Shay Aisman

IPC: G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G06F12/1045 ,  G06F15/173 ,  G06F9/46 ,  G06F9/455

Abstract: A computing system includes at least one peripheral bus, a peripheral device connected to the at least one peripheral bus, at least one memory, and first and second system components. The first system component is (i) associated with a first address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The second system component is (i) associated with a second address space in the at least one memory and (ii) connected to the peripheral device via the at least one peripheral bus. The first system component is arranged to cause the peripheral device to access the second address space that is associated with the second system component.

公开(公告)号：US11388263B2

公开(公告)日：2022-07-12

申请号：US17067690

申请日：2020-10-11

Applicant: MELLANOX TECHNOLOGIES, LTD.

Inventor： Dotan David Levi ,  Daniel Marcovitch ,  Lior Narkis ,  Avi Urman

IPC: H04L49/90 ,  H04L67/5681 ,  H04W72/12

Abstract: A Network-Connected Device (NCD) includes a network interface, a host interface, an NCD memory and an NCD processor. The network interface is configured for communicating over a network. The host interface is configured for communicating with a host. The NCD memory is configured to buffer packet information that originates from the host and pertains to a packet to be transmitted to the network at a specified transmission time. The NCD processor is configured to process the buffered packet information before the specified transmission time, and to transmit the packet to the network at the specified time. Processing of the packet information and transmission of the packet are decoupled from buffering of the packet information.