Adding a Network Port to a Network Interface Card

    公开(公告)号:US20180239730A1

    公开(公告)日:2018-08-23

    申请号:US15896092

    申请日:2018-02-14

    Inventor: Yuval Itkin

    CPC classification number: G06F13/385 G06F13/4221 G06F2213/3808 H04L67/125

    Abstract: A host computer connects to a data network via a host interface to a network interface controller A sideband interface connects the network interface controller to a baseboard management controller having a management network port for connection to a management network. A path is established in the network interface controller between the host interface the basement management controller via the sideband interface of the network interface controller to conduct data selectively between the management network and either the host central processing unit and the or internally in the network interface controller.

    Remote host management over a network
    22.
    发明申请

    公开(公告)号:US20170242819A1

    公开(公告)日:2017-08-24

    申请号:US15051750

    申请日:2016-02-24

    CPC classification number: G06F13/42 G06F13/36 G06F13/4027

    Abstract: A method for management of a host computer that includes a management controller configured to carry out, independently of the host CPU, host management instructions contained in management packets compliant with a first data link protocol. The method includes receiving the management packets from a first network operating in accordance with the first data link protocol. The management packets are encapsulated in data packets compliant with a second data link protocol, different from the first data link protocol. The data packets are transmitted to a second network, operating in accordance with the second data link protocol. The transmitted data packets are received from the second network in a network interface controller (NIC), which is installed in the host computer and connected to the second network. The NIC decapsulates the management packets from the received data packets and passes the decapsulated management packets via a sideband connection to the management controller.

    Peripheral device with cache updating from multiple sources

    公开(公告)号:US20250077429A1

    公开(公告)日:2025-03-06

    申请号:US18950269

    申请日:2024-11-18

    Abstract: A peripheral device includes a processor, a memory interface, a host interface and a cache controller. The processor executes software code. The cache memory caches a portion of the software code. The memory interface communicates with a NVM storing a replica of the software code. The host interface communicates with hosts storing additional replicas of the software code. The cache controller is to determine whether each host is allocated for code fetching, to receive a request from the processor for a segment of the software code, when available in the cache memory to fetch the segment from the cache memory, when unavailable in the cache memory and at least one host is allocated, to fetch the segment from the hosts that are allocated, when unavailable in the cache memory and no host is allocated, to fetch the segment from the NVM, and to serve the fetched segment to the processor.

    Secure in-service firmware update
    24.
    发明授权

    公开(公告)号:US12223051B2

    公开(公告)日:2025-02-11

    申请号:US18349147

    申请日:2023-07-09

    Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

    Secure In-Service Firmware Update
    25.
    发明公开

    公开(公告)号:US20230351021A1

    公开(公告)日:2023-11-02

    申请号:US18349147

    申请日:2023-07-09

    CPC classification number: G06F21/572 G06F8/65 G06F9/445 G06F2221/033

    Abstract: A computer system includes a volatile memory and at least one processor. The volatile memory includes a protected storage segment (PSS) configured to store firmware-authentication program code for authenticating firmware of the computer system. The at least one processor is configured to receive a trigger to switch to a given version of the firmware, to obtain, in response to the trigger, a privilege to access the PSS, to authenticate the given version of the firmware by executing the firmware-authentication program code from the PSS, to switch to the given version of the firmware upon successfully authenticating the given version, and to take an alternative action upon failing to authenticate the given version.

    Secure remote reset
    26.
    发明公开
    Secure remote reset 审中-公开

    公开(公告)号:US20230297669A1

    公开(公告)日:2023-09-21

    申请号:US17694725

    申请日:2022-03-15

    Inventor: Yuval Itkin

    Abstract: In one embodiment, a system includes data communication device including a network interface to receive a nonce supply request from a remote machine, processing core(s), processing circuitry to generate a nonce, sign the nonce with a private key of the data communication device yielding a first digital signature, provide the nonce and first digital signature to the remote machine, receive, from the remote machine, a secure reset request including a second digital signature of the nonce signed with a private key of the remote machine, verify the second digital signature with a public key of the remote machine to verify that the remote machine provided the secure reset request and that the nonce signed by the second digital signature is the same nonce provided to the remote machine, and issue a reset command to the processing core(s) to reboot responsively to the verification of the second digital signature.

    Network-adapter configuration using option-ROM in multi-CPU devices

    公开(公告)号:US11055104B2

    公开(公告)日:2021-07-06

    申请号:US16660838

    申请日:2019-10-23

    Abstract: A network adapter includes one or more network ports, multiple bus interfaces and a processor. The network ports are configured to communicate with a communication network. The bus interfaces are configured to communicate with multiple respective CPUs of a multi-CPU device. The processor is included in the network adapter and is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, to expose the support of the Option-ROM functionality to the multi-CPU device over only a single bus interface, selected from among the multiple bus interfaces, and, by loading the Option-ROM program instructions to the multi-CPU device, to cause the multi-CPU device to present to a user only a single, non-redundant set of commands for managing all the multiple bus interfaces of the network adapter via the single bus interface.

    Network-Adapter Configuration using Option-ROM in Multi-CPU Devices

    公开(公告)号:US20210124590A1

    公开(公告)日:2021-04-29

    申请号:US16660838

    申请日:2019-10-23

    Abstract: A network adapter includes one or more network ports, multiple bus interfaces and a processor. The network ports are configured to communicate with a communication network. The bus interfaces are configured to communicate with multiple respective CPUs of a multi-CPU device. The processor is included in the network adapter and is configured to support an Option-ROM functionality, in which the network adapter holds Option-ROM program instructions that are loadable and executable by the multi-CPU device during a boot process, to expose the support of the Option-ROM functionality to the multi-CPU device over only a single bus interface, selected from among the multiple bus interfaces, and, by loading the Option-ROM program instructions to the multi-CPU device, to cause the multi-CPU device to present to a user only a single, non-redundant set of commands for managing all the multiple bus interfaces of the network adapter via the single bus interface.

    Secure boot
    30.
    发明授权

    公开(公告)号:US10984107B2

    公开(公告)日:2021-04-20

    申请号:US15960576

    申请日:2018-04-24

    Inventor: Yuval Itkin

    Abstract: A method for secure boot includes, in a processor, retrieving from a memory device a firmware boot code for bootstrapping a firmware of the processor. The firmware boot code is authenticated using an authentication key. In response to failing to authenticate the firmware boot code using the authentication key, an attempt is made to authenticate a recovery firmware code, which has reduced functionality relative to the firmware boot code, using a recovery key. Upon successfully authenticating the recovery firmware code using the recovery key, the firmware boot code is restored from a host, the restored firmware boot code is authenticated by executing the recovery firmware code, and the firmware is bootstrapped using the authenticated firmware boot code.

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