ENHANCED MICROPROCESSOR OR MICROCONTROLLER
    21.
    发明申请
    ENHANCED MICROPROCESSOR OR MICROCONTROLLER 审中-公开
    增强微处理器或MICROCONTROLLER

    公开(公告)号:US20140019991A1

    公开(公告)日:2014-01-16

    申请号:US14028458

    申请日:2013-09-16

    CPC classification number: G06F9/461

    Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

    Abstract translation: 微控制器设备具有中央处理单元(CPU); 与分配到多个存储体中的CPU耦合的数据存储器,可以被存储器映射的多个特殊功能寄存器和通用寄存器,其中至少以下特殊功能寄存器被存储器映射到所有存储体状态 寄存器,存储体选择寄存器,多个间接存储器地址寄存器,工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时,所述CPU可操作以自动保存状态寄存器,存储体选择寄存器,多个间接存储器地址寄存器,工作寄存器和程序计数器高锁存器的内容,并且在返回时 从上下文切换恢复状态寄存器,存储体选择寄存器,多个间接存储器地址寄存器,工作寄存器和程序计数器高锁存器的内容。

    Direct memory access adapter
    22.
    发明授权

    公开(公告)号:US10360164B1

    公开(公告)日:2019-07-23

    申请号:US15944772

    申请日:2018-04-03

    Abstract: A processor includes a central processing unit (CPU) and a direct memory access (DMA) adapter circuit. The DMA adapter circuit includes a DMA controller circuit and is configured to interface with a legacy internal hardware peripheral and with a DMA-enabled internal hardware peripheral. The DMA-enabled internal hardware peripheral includes a first special function register (SFR). The legacy internal hardware peripheral includes no DMA features. The CPU is configured to execute a legacy application that accesses a setting in memory through the legacy internal hardware peripheral. Execution of the legacy application includes access by the CPU of the setting in memory. The DMA controller circuit is configured to access the setting in memory during execution of a DMA-enabled application through the DMA-enabled internal hardware peripheral.

    Current sensing with internal ADC capacitor

    公开(公告)号:US09823280B2

    公开(公告)日:2017-11-21

    申请号:US13709399

    申请日:2012-12-10

    Inventor: Joseph Julicher

    CPC classification number: G01R19/25 G01N21/53 G08B17/103 G08B29/24

    Abstract: External conditions, e.g., smoke, temperature, humidity, humidity, pressure, flow rate, etc., affects a sensor's characteristics, wherein the sensor provides a current output representative of its characteristics as affected by the external conditions. The current output of the sensor is coupled to a sample and hold capacitor for a precision time period thereby charging the sample and hold capacitor to a voltage proportional to current provided by the sensor over the precision time period. The voltage on the sample and hold capacitor is converted to a digital representation and a determination is made whether the external condition represents an alarm situation, e.g., smoke detected from a fire.

    RAMP GENERATION MODULE
    25.
    发明申请
    RAMP GENERATION MODULE 审中-公开
    RAMP生成模块

    公开(公告)号:US20150303902A1

    公开(公告)日:2015-10-22

    申请号:US14669321

    申请日:2015-03-26

    CPC classification number: H03K4/50 H03K4/502

    Abstract: A digitally controlled ramp generator has a constant current source, a first controllable switch coupled between the constant current source and an output node, a capacitor coupled with the output node, a second controllable switch coupled with the output node, a constant current sink coupled with the second controllable switch, and a control unit. The control unit is configured in a first operating mode to select control signals for the first and second controllable switch to generate a rising waveform by charging said capacitor through the first controllable switch and a falling waveform by discharging the capacitor through the second controllable switch wherein the control signals can be selected from the group of a time based control signal and a voltage based control signal. A variety of other control modes may be provided.

    Abstract translation: 数字控制的斜坡发生器具有恒定电流源,耦合在恒定电流源和输出节点之间的第一可控开关,与输出节点耦合的电容器,与输出节点耦合的第二可控开关,与 第二可控开关和控制单元。 控制单元被配置为第一操作模式,以通过第一可控开关对所述电容器充电以及通过第二可控开关放电电容器来产生下降波形来选择第一和第二可控开关的控制信号,以产生上升波形,其中, 可以从基于时间的控制信号和基于电压的控制信号的组中选择控制信号。 可以提供各种其他控制模式。

    Method and Apparatus for Detecting Smoke in an ION Chamber
    26.
    发明申请
    Method and Apparatus for Detecting Smoke in an ION Chamber 有权
    在离子室中检测烟雾的方法和装置

    公开(公告)号:US20130154670A1

    公开(公告)日:2013-06-20

    申请号:US13667269

    申请日:2012-11-02

    CPC classification number: G08B17/11 G01N27/66 G01R27/2605

    Abstract: A smoke detection sensor ion chamber has a capacitance and a change in the permittivity of that capacitance dielectric (ionized air in the chamber) may be used to detect the presence of smoke therein. Smoke from typical fires is mainly composed of unburned carbon that has diffused in the surrounding air and rises with the heat of the fire. The permittivity of the carbon particles is about 10 to 15 times the permittivity of clean air. The addition of the carbon particles into the air in the ion chamber changes in the permittivity thereof that is large enough to measure by measuring a change in capacitance of the ion chamber.

    Abstract translation: 烟雾检测传感器离子室具有电容并且可以使用该电容电介质(室中的电离空气)的介电常数的变化来检测其中的烟雾的存在。 典型火灾中的烟雾主要由在周围空气中扩散并随火的升高而升高的未燃碳组成。 碳颗粒的介电常数为清洁空气介电常数的约10至15倍。 将离子室中的碳颗粒加入到空气中,通过测量离子室的电容变化来测量介电常数,其电容率变大。

    Direct Memory Access Adapter
    27.
    发明申请

    公开(公告)号:US20190227966A1

    公开(公告)日:2019-07-25

    申请号:US15944772

    申请日:2018-04-03

    Abstract: A processor includes a central processing unit (CPU) and a direct memory access (DMA) adapter circuit. The DMA adapter circuit includes a DMA controller circuit and is configured to interface with a legacy internal hardware peripheral and with a DMA-enabled internal hardware peripheral. The DMA-enabled internal hardware peripheral includes a first special function register (SFR). The legacy internal hardware peripheral includes no DMA features. The CPU is configured to execute a legacy application that accesses a setting in memory through the legacy internal hardware peripheral. Execution of the legacy application includes access by the CPU of the setting in memory. The DMA controller circuit is configured to access the setting in memory during execution of a DMA-enabled application through the DMA-enabled internal hardware peripheral.

    Programmable Driver For Single Phase Brushless DC (BLDC) Motor With Hall Sensor

    公开(公告)号:US20180234036A1

    公开(公告)日:2018-08-16

    申请号:US15885994

    申请日:2018-02-01

    CPC classification number: H02P6/06 H02P6/17 H02P6/26 H02P6/28

    Abstract: A BLDC motor drive system may be configured to provide a programmable PWM current waveform, e.g., a sinusoidal PWM current, to the motor. The drive system may include control electronics configured to generate a series of PWM control signals at a control signal frequency based on (a) the present motor speed data as determined by an angular timer, based on sensor-based rotor angle data, (b) a target motor speed, e.g., based on a thermal management unit, and (c) stored current waveform data defining a target current for each angular segment of the BDLC rotor, the target currents defining an non-rectangular waveform shape. The PWM control signals are used by a PWM unit to produce a non-rectangular, e.g., sinusoidal, PWM current for controlling the BDLC.

    Differential current measurements to determine ion current in the presence of leakage current

    公开(公告)号:US09805572B2

    公开(公告)日:2017-10-31

    申请号:US14967930

    申请日:2015-12-14

    CPC classification number: G08B17/11 G01N27/66 G08B17/113

    Abstract: An ion chamber provides a current representative of its characteristics as affected by external conditions, e.g., clean air or smoke. A direct current (DC) voltage is applied to the ion chamber at a first polarity and the resulting current through the ion chamber and parasitic leakage current is measured at the first polarity, then the DC voltage is applied to the ion chamber at a second polarity opposite the first polarity, and the resulting current through the ion chamber and parasitic leakage current is measured at the second polarity. Since substantially no current flows through the ion chamber at the second polarity, the common mode parasitic leakage current contribution may be removed from the total current measurement by subtracting the current measured at the second polarity from the current measured at the first polarity, resulting in just the current through the ion chamber.

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