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    Floating body field-effect transistors, and methods of forming floating body field-effect transistors
    21.
    发明授权
    Floating body field-effect transistors, and methods of forming floating body field-effect transistors 有权
    浮体场效应晶体管，以及形成浮体场效应晶体管的方法

    公开(公告)号：US08716075B2

    公开(公告)日：2014-05-06

    申请号：US13761587

    申请日：2013-02-07

    Applicant: Micron Technology, Inc.

    Inventor： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

    IPC: H01L21/00 ,  H01L21/84

    CPC classification number: H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

    Abstract translation: 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

    Memory Cells, And Methods Of Forming Memory Cells
    22.
    发明申请
    Memory Cells, And Methods Of Forming Memory Cells 有权
    记忆细胞和形成记忆细胞的方法

    公开(公告)号：US20130126908A1

    公开(公告)日：2013-05-23

    申请号：US13717465

    申请日：2012-12-17

    Applicant: Micron Technology, Inc.

    Inventor： Chandra Mouli

    IPC: H01L29/78 ,  H01L29/16

    CPC classification number: H01L29/7841 ,  H01L27/1021 ,  H01L27/10802 ,  H01L29/1608

    Abstract: Some embodiments include memory cells that contain floating bodies and diodes. The diodes may be gated diodes having sections doped to a same conductivity type as the floating bodies, and such sections of the gated diodes may be electrically connected to the floating bodies. The floating bodies may be adjacent channel regions, and spaced from the channel regions by a dielectric structure. The dielectric structure of a memory cell may have a first portion between the floating body and the diode, and may have a second portion between the floating body and the channel region. The first portion may be more leaky to charge carriers than the second portion. The diodes may be formed in semiconductor material that is different from a semiconductor material that the channel regions are in. The floating bodies may have bulbous lower regions. Some embodiments include methods of making memory cells.

    Abstract translation: 一些实施例包括含有浮体和二极管的存储单元。 二极管可以是具有掺杂到与浮体相同的导电类型的部分的门极二极管，并且门控二极管的这些部分可以电连接到浮体。 浮体可以是相邻的沟道区，并且通过电介质结构与沟道区隔开。 存储单元的电介质结构可以具有在浮体和二极管之间的第一部分，并且可以在浮体和沟道区之间具有第二部分。 与第二部分相比，第一部分对于载流子的泄漏可能更多。 二极管可以形成为不同于沟道区域的半导体材料的半导体材料。浮体可以具有球形的下部区域。 一些实施例包括制造存储器单元的方法。

    Apparatuses having body connection lines coupled with access devices
    27.
    发明授权
    Apparatuses having body connection lines coupled with access devices 有权

    公开(公告)号：US10269805B2

    公开(公告)日：2019-04-23

    申请号：US15895928

    申请日：2018-02-13

    Applicant: Micron Technology, Inc.

    Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Chandra Mouli ,  Sanh D. Tang

    IPC: G11C5/02 ,  G11C5/06 ,  H01L27/108 ,  H01L29/78

    Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

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