公开(公告)号：US20140252449A1

公开(公告)日：2014-09-11

申请号：US14223410

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra V. Mouli ,  Di Li

IPC: H01L29/788 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Abstract translation: 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

公开(公告)号：US08729621B2

公开(公告)日：2014-05-20

申请号：US14048151

申请日：2013-10-08

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L27/108

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20140035021A1

公开(公告)日：2014-02-06

申请号：US14048151

申请日：2013-10-08

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L29/66 ,  H01L21/22 ,  H01L21/265 ,  H01L29/788

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20140051214A1

公开(公告)日：2014-02-20

申请号：US13761587

申请日：2013-02-07

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

IPC: H01L27/12 ,  H01L27/108 ,  H01L29/66

CPC classification number: H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract translation: 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

公开(公告)号：US08580645B2

公开(公告)日：2013-11-12

申请号：US13786889

申请日：2013-03-06

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L21/336

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US09356157B2

公开(公告)日：2016-05-31

申请号：US14223410

申请日：2014-03-24

Applicant: Micron Technology, Inc.

Inventor： Gurtej S. Sandhu ,  Chandra V. Mouli ,  Di Li

IPC: H01L29/788 ,  H01L51/52 ,  H01L51/56 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/788 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/42376 ,  H01L29/66825 ,  H01L29/7883 ,  H01L51/5253 ,  H01L51/56

Abstract: Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.

Abstract translation: 半导体器件包括具有浮置栅极和控制栅极的一个或多个晶体管。 在至少一个实施例中，浮动门包括在两个端部之间延伸的中间部分。 中间部分具有小于一个或两个端部的平均横截面面积。 在一些实施例中，中间部分可以包括单个纳米线。 在另外的实施例中，半导体器件具有一个或多个具有控制栅极和浮置栅极的晶体管，其中控制栅极的表面与浮置栅极的限定了浮动栅极中的凹部的横向侧表面相对。 电子系统包括这样的半导体器件。 形成半导体器件的方法包括例如形成具有在两个端部之间延伸的中间部分的浮动栅极，并且将中间部分构造成具有小于一个或两个端部的平均横截面积。

公开(公告)号：US08716075B2

公开(公告)日：2014-05-06

申请号：US13761587

申请日：2013-02-07

Applicant: Micron Technology, Inc.

Inventor： Jun Liu ,  Michael P. Violette ,  Chandra Mouli ,  Howard Kirsch ,  Di Li

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L27/10802 ,  H01L29/66477 ,  H01L29/7841 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a floating body field-effect transistor includes a pair of source/drain regions having a floating body channel region received therebetween. The source/drain regions and the floating body channel region are received over an insulator. A gate electrode is proximate the floating body channel region. A gate dielectric is received between the gate electrode and the floating body channel region. The floating body channel region has a semiconductor SixGe(1-x)-comprising region. The floating body channel region has a semiconductor silicon-comprising region received between the semiconductor SixGe(1-x)-comprising region and the gate dielectric. The semiconductor SixGe(1-x)-comprising region has greater quantity of Ge than any quantity of Ge within the semiconductor silicon-comprising region. Other embodiments are contemplated, including methods of forming floating body field-effect transistors.

Abstract translation: 在一个实施例中，浮体场效应晶体管包括一对在其间容纳浮体通道区的源/漏区。 源极/漏极区域和浮体沟道区域被接纳在绝缘体上。 栅电极靠近浮体通道区域。 门电介质被接收在栅电极和浮体沟道区之间。 浮体通道区域具有半导体SixGe（1-x）区域。 浮体通道区域具有容纳在半导体SixGe（1-x）区域和栅极电介质之间的半导体硅包覆区域。 半导体SixGe（1-x）含量区域在含半导体硅的区域内具有比任何Ge量更大的Ge量。 考虑了其他实施例，包括形成浮体场效应晶体管的方法。

公开(公告)号：US20130193505A1

公开(公告)日：2013-08-01

申请号：US13786889

申请日：2013-03-06

Applicant: Micron Technology, Inc.

Inventor： Kirk D. Prall ,  Behnam Moradi ,  Seiichi Aritome ,  Di Li ,  Chris Larsen

IPC: H01L27/105

CPC classification number: H01L29/66825 ,  H01L21/22 ,  H01L21/265 ,  H01L21/26506 ,  H01L21/324 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/6659 ,  H01L29/66659 ,  H01L29/788

Abstract: Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

Abstract translation: 公开了一种使用卤素离子注入和扩散工艺形成存储器件的方法。 在一个说明性实施例中，该方法包括在半导体衬底上形成多个字线结构，每个字线结构包括栅极绝缘层，执行LDD离子注入工艺，以在字线之间的衬底中形成LDD掺杂区域 结构，执行卤素离子注入工艺，以将卤素原子植入到半导体衬底中的字线结构之间，以及执行至少一个退火工艺以使至少一些卤素原子扩散到相邻字的栅极绝缘层中 线结构。

公开(公告)号：US20140254265A1

公开(公告)日：2014-09-11

申请号：US14282810

申请日：2014-05-20

Applicant: Micron Technology, Inc.

Inventor： Seiichi Aritome ,  Di Li

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: Some embodiments include utilization of alternating first and second gate types along NAND strings, with the second gate types having floating gates thicker than floating gates of the first gate types, and capacitively coupled with control gates of the first gate types. The second gate types may be multilevel cell (MLC) devices, and pass voltage applied to the control gates of the first gate types may be utilized to reduce programming voltages utilized to reach memory states of the MLC devices. Some embodiments include NAND cell units, and some embodiments include methods of forming NAND cell units. Also, some embodiments include methods of programming NAND cell unit string gates in which programming voltage applied to a first string gate is held below a threshold, and pass voltage applied to an adjacent string gate is increased and utilized to program the first string gate.

Abstract translation: 一些实施例包括沿NAND串的交替的第一和第二栅极类型的利用，其中第二栅极类型具有比第一栅极类型的浮置栅极厚的浮动栅极，并且与第一栅极类型的栅极电容耦合。 第二栅极类型可以是多电平单元（MLC）器件，并且施加到第一栅极类型的控制栅极的通过电压可以用于减少用于达到MLC器件的存储器状态的编程电压。 一些实施例包括NAND单元单元，并且一些实施例包括形成NAND单元单元的方法。 此外，一些实施例包括编程NAND单元单元串门的方法，其中施加到第一串门的编程电压被保持在阈值以下，并且增加施加到相邻串门的通过电压并用于对第一串门进行编程。